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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 112 powerful instructions ? most single clock cycle execution ? 16 x 8 general purpose working registers ? fully static operation ? up to 12 mips throughput at 12 mhz ? non-volatile program and data memories ? 2k bytes of in-system programmable flash program memory ? 128 bytes internal sram ? flash write/erase cycles: 10,000 ? data retention: 20 years at 85 o c / 100 years at 25 o c ? peripheral features ? one 8-bit timer/counte r with two pwm channels ? one 16-bit timer/counter with two pwm channels ? 10-bit analog to digital converter ? 8 single-ended channels ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? master/slave spi serial interface ? slave twi serial interface ? special microcontroller features ? in-system programmable ? external and internal interrupt sources ? low power idle, adc noise reduction, stand-by and power-down modes ? enhanced power-on reset circuit ? internal calibrated oscillator ? i/o and packages ? 14-pin soic/tssop: 12 programmable i/o lines ? 15-ball ufbga: 12 programmable i/o lines ? 20-pad vqfn: 12 programmable i/o lines ? operating voltage: ? 1.8 ? 5.5v ? programming voltage: ?5v ? speed grade ? 0 ? 4 mhz @ 1.8 ? 5.5v ? 0 ? 8 mhz @ 2.7 ? 5.5v ? 0 ? 12 mhz @ 4.5 ? 5.5v ? industrial temperature range ? low power consumption ? active mode: ? 200 a at 1 mhz and 1.8v ?idle mode: ? 25 a at 1 mhz and 1.8v ? power-down mode: ? < 0.1 a at 1.8v 8-bit microcontroller with 2k bytes in-system programmable flash attiny20 rev. 8235b?avr?04/11
2 8235b?avr?04/11 attiny20 1. pin configurations figure 1-1. pinout of attiny20 1.1 pin description 1.1.1 vcc supply voltage. 1.1.2 gnd ground. table 1-1. pinout attiny20 in ufbga. 1234 a pa 5 pa 6 p b 2 b pa4 pa7 pb1 pb3 c pa 3 pa 2 pa 1 p b 0 d pa0 gnd gnd vcc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 vcc (pcint8/tpiclk/t0/clki) pb0 (pcint9/tpidata/mosi/sda/oc1a) pb1 (pcint11/reset) pb3 (pcint10/int0/miso/oc1b/oc0a/ckout) pb2 (pcint7/scl/sck/t1/icp1/oc0b/adc7) pa7 (pcint6/ss/adc6) pa6 gnd pa0 (adc0/pcint0) pa1 (adc1/ain0/pcint1) pa2 (adc2/ain1/pcint2) pa3 (adc3/pcint3) pa4 (adc4/pcint4) pa5 (adc5/pcint5) soic/tssop 1 2 3 4 5 vqfn 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 note bottom pad should be soldered to ground. dnc: do not connect dnc dnc gnd vcc dnc pa7 (adc7/oc0b/icp1/t1/scl/sck/pcint7) pb2 (ckout/oc0a/oc1b/miso/int0/pcint10) pb3 (reset/pcint11) pb1 (oc1a/sda/mosi/tpidata/pcint9) pb0 (clki/t0/tpiclk/pcint8) dnc dnc dnc pa5 pa6 pin 16: pa6 (adc6/ss/pcint6) pin 17: pa5 (adc5/pcint5) (pcint4/adc4) pa4 (pcint3/adc3) pa3 (pcint2/ain1/adc2) pa2 (pcint1/ain0/adc1) pa1 (pcint0/adc0) pa0 3 8235b?avr?04/11 attiny20 1.1.3 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and prov ided the reset pin has not been disabled. the min- imum pulse length is given in table 20-4 on page 175 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 1.1.4 port a (pa7:pa0) port a is a 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a has alternate functions as analog inputs for the adc, analog comparator and pin change interrupt as described in ?alternate port functions? on page 49 . 1.1.5 port b (pb3:pb0) port b is a 4-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability except pb3 which has the reset capability. to use pin pb3 as an i/o pin, instead of reset pin, program (?0?) rstdisbl fuse. as inpu ts, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. the port also serves the functions of various special features of the attiny20, as listed on page 39 . 4 8235b?avr?04/11 attiny20 2. overview attiny20 is a low-power cmos 8-bit microcontroller based on the compact avr enhanced risc architecture. by executing powerful instru ctions in a single clock cycle, the attiny20 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. figure 2-1. block diagram the avr core combines a rich instruction set with 16 general purpose working registers and system registers. all registers are directly connect ed to the arithmetic lo gic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. stack pointer sram program counter programming logic isp interface internal oscillator watchdog timer reset flag register mcu status register timer/ counter0 calibrated oscillator timing and control interrupt unit analog comparator adc general purpose registers x y z alu status register program flash instruction register instruction decoder control lines v cc reset data register port a direction reg. port a drivers port a gnd pa[7:0] 8-bit data bus timer/ counter1 twi spi data register port b direction reg. port b drivers port b pb[3:0] 5 8235b?avr?04/11 attiny20 the resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. attiny20 provides the following features: ? 2k bytes of in-system programmable flash ? 128 bytes of sram ? twelve general purpose i/o lines ? 16 general purpose working registers ? an 8-bit timer/counter with two pwm channels ? a 16-bit timer/counter with two pwm channels ? internal and external interrupts ? an eight-channel, 10-bit adc ? a programmable watchdog timer with internal oscillator ? a slave two-wire interface ? a master/slave serial peripheral interface ? an internal calibrated oscillator ? four software selectable power saving modes the device includes the following modes for saving power: ? idle mode: stops the cpu while allowing the timer/counter, adc, analog comparator, spi, twi, and interrupt system to continue functioning ? adc noise reduction mode: minimizes switching noise during adc conversions by stopping the cpu and all i/o modules except the adc ? power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset ? standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on- chip, in-system programmable flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. the attiny20 avr is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 6 8235b?avr?04/11 attiny20 3. general information 3.1 resources a comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. 3.3 capacitive touch sensing atmel qtouch library provides a simple to use solution for touch sensitive interfaces on atmel avr microcontrollers. the qtouch library includes support for qtouch ? and qmatrix ? acquisi- tion methods. touch sensing is easily added to any application by linking the qtouch library and using the application programming interface (api) of the library to define the touch channels and sensors. the application then calls the api to retrieve channel information and determine the state of the touch sensor. the qtouch library is free and can be downloaded from the atmel website. for more informa- tion and details of implementation, refer to the qtouch library user guide ? also available from the atmel website. 3.4 data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 3.5 disclaimer typical values contained in this datasheet ar e based on simulations and characterization of other avr microcontrollers manufactured on the same process technology. 7 8235b?avr?04/11 attiny20 4. cpu core this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 architectural overview figure 4-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 16 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. flash program memory instruction register instruction decoder program counter control lines 16 x 8 general purpose registrers alu status and control i/o lines data bus 8-bit data sram direct addressing indirect addressing interrupt unit watchdog timer analog comparator timer/counter 0 adc twi slave spi timer/counter 1 8 8235b?avr?04/11 attiny20 six of the 16 registers can be used as three 16- bit indirect address register pointers for data space addressing ? enabling efficient address calc ulations. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. most avr instructions have a single 16-bit word format but 32-bit wide instructions also exist. th e actual instruction set varies, as some devices only implement a part of the instruction set. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the sram size and the usage of the sram. all user programs must initial- ize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the four different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses fo r cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed as the data space locations, 0x0000 - 0x003f. 4.2 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 16 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see document ?avr instruction set? and section ?instruction set sum- mary? on page 210 for a detailed description. 4.3 status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in document ?avr instruction set? and section ?instruction set summary? on page 210 . this will in many cases remove the need fo r using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 9 8235b?avr?04/11 attiny20 4.4 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? one 16-bit output operand and one 16-bit result input figure 4-2 below shows the structure of the 16 general purpose working registers in the cpu. figure 4-2. avr cpu general purpose working registers note: a typical implementation of the avr register file includes 32 general prupose registers but attiny20 implements only 16 registers. for r easons of compatibility the registers are numbered r16:r31 and not r0:r15. most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. 4.4.1 the x-register, y-register, and z-register registers r26:r31 have some added functions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 4-3 . 70 r16 r17 general r18 purpose ? working r26 x-register low byte registers r27 x-register high byte r28 y-register low byte r29 y-register high byte r30 z-register low byte r31 z-register high byte 10 8235b?avr?04/11 attiny20 figure 4-3. the x-, y-, and z-registers in different addressing modes these address registers function as automatic increment and automatic decrement (see document ?avr instruction set? and section ?instruction set sum- mary? on page 210 for details). 4.5 stack pointer the stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls. the stack pointer registers (sph and spl) always point to the top of the stack. note that the stack grows from higher memory locations to lower memory loca- tions. this means that the push instructions decreases and the pop instruction increases the stack pointer value. the stack pointer points to the area of data me mory where subroutine and interrupt stacks are located. this stack space must be defined by the program before any subroutine calls are exe- cuted or interrupts are enabled. the pointer is decremented by one when data is put on the stack with the push instruction, and incremented by one when data is fetched with the pop instruction. it is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the ret instruction) or a return from interrupt service routine (the reti instruction). the avr stack pointer is typically implemented as two 8-bit registers in the i/o register file. the width of the stack pointer and the number of bits implemented is device dependent. in some avr devices all data memory can be addressed us ing spl, only. in this case, the sph register is not implemented. the stack pointer must be set to point above the i/o register areas, the minimum value being the lowest address of sram. see figure 5-1 on page 16 . 4.6 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. 15 xh xl 0 x-register 707 0 r27 r26 15 yh yl 0 y-register 707 0 r29 r28 15 zh zl 0 z-register 707 0 r31 r30 11 8235b?avr?04/11 attiny20 figure 4-4. the parallel instruction fetches and instruction executions figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 4-5. single cycle alu operation 4.7 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 38 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 12 8235b?avr?04/11 attiny20 interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt fl ag will be set and remember ed until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is clea red, the corres ponding interrupt fl ag(s) will be set and remembered until the global interrupt enable bit is set, and will then be exec uted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction before any pending interrupt is served. note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. when using the sei instruction to enable interr upts, the instruction following sei will be exe- cuted before any pending interrupts, as shown in the following example. note: see ?code examples? on page 6 . 4.7.1 interrupt response time the interrupt execution response for all the enabl ed avr interrupts is four clock cycles mini- mum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi- cycle instruction, this in struction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine take s four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) 13 8235b?avr?04/11 attiny20 4.8 register description 4.8.1 ccp ? configuration change protection register ? bits 7:0 ? ccp[7:0]: configuration change protection in order to change the contents of a protected i/o register the ccp register must first be written with the correct signature. after ccp is written the protected i/o registers may be written to dur- ing the next four cpu instruction cycles. all in terrupts are ignored during these cycles. after these cycles interrupts are automatically handled again by the cpu, and any pending interrupts will be executed according to their priority. when the protected i/o register signature is wri tten, ccp0 will read as one as long as the pro- tected feature is enab led, while ccp[7:1] will always read as zero. table 4-1 shows the signatures that are in recognised. notes: 1. only wde and wdp[3:0] bits are protected in wdtcsr. 2. only bods bit is protected in mcucr. 4.8.2 sph and spl ? stack pointer registers ? bits 7:0 ? sp[7:0]: stack pointer the stack pointer register points to the top of the stack, which is implemented growing from higher memory locations to lower memory locations. hence, a stack push command decreases the stack pointer. the stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. in attiny20, the sph register has not been implemented. bit 76543210 0x3c ccp[7:0] ccp read/write wwwwwwwr/w initial value00000000 table 4-1. signatures recognised by the configuration change protection register signature group description 0xd8 ioreg: clkmsr, clkpsr, wdtcsr (1) , mcucr (2) protected i/o register initial value 00000000 read/write rrrrrrrr bit 151413121110 9 8 0x3e ? ? ?????? sph 0x3d sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl bit 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend ramend ramend ramend ramend ramend ramend 14 8235b?avr?04/11 attiny20 4.8.3 sreg ? status register ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for th e interrupts to be enabled. the individual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the document ?avr instruction set? and ?instruction set summary? on page 210 . ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operation s. half carry is useful in bcd arithmetic. see document ?avr instruction set? and section ?instruction set summary? on page 210 for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see document ?avr instruction set? and section ?instruction set summary? on page 210 for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see document ?avr instruction set? and section ?instruction set summary? on page 210 for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see docu- ment ?avr instruction set? and section ?instruction set summary? on page 210 for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see document ?avr instruction set? and section ?instruction set summary? on page 210 for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see document ?avr instruction set? and section ?instruction set summary? on page 210 for detailed information. bit 76543210 0x3f i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 15 8235b?avr?04/11 attiny20 5. memories this section describes the different memories in the attiny20. the device has two main memory areas, the program memory space and the data memory space. 5.1 in-system re-programmable flash program memory the attiny20 contains 2k byte on-chip, in- system reprogrammable flas h memory for program storage. since all avr instructions are 16 or 32 bits wide, the flash is organized as 1024 x 16. the flash memory has an endurance of at least 10,000 write/erase cycles. the attiny20 pro- gram counter (pc) is 10 bits wide, thus capable of addressing the 1024 program memory locations, starting at 0x000. ?memory programming? on page 163 contains a detailed description on flash data serial downloading. constant tables can be allocated within the enti re address space of program memory. since pro- gram memory can not be accessed directly, it has been mapped to the data memory. the mapped program memory begins at byte address 0x4000 in data memory (see figure 5-1 on page 16 ). although programs are executed starting from address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data memory. internal write operations to flash program memory have been disabled and program memory therefore appea rs to firmware as r ead-only. flash memory can still be written to externally but internal write operations to the program memory ar ea will not be succesful. timing diagrams of instruction fetch and execution are presented in ?instruction execution tim- ing? on page 10 . 5.2 data memory data memory locations include the i/o memory, the internal sram memory, the non-volatile memory lock bits, and the flash memory. see figure 5-1 on page 16 for an illustration on how the attiny20 memory space is organized. the first 64 locations are reserved for i/o memory, while the following 128 data memory loca- tions (from 0x0040 to 0x00bf) address the internal data sram. the non-volatile memory lock bits and all the flash memory sections are mapped to the data memory space. these locations appear as read-only for device firmware. the four different addressing modes for data memory are direct, indirect, indirect with pre-decre- ment, and indirect with post-increment. in the register file, registers r26 to r31 function as pointer registers for indirect addressing. the in and out instructions can access all 64 locations of i/o memory. direct addressing using the lds and sts instructions reaches the 128 locations between 0x0040 and 0x00bf. the indirect addressing reaches the entire data memory space. when using indirect addressing modes with automatic pre-decrement and post-increment, the address registers x, y, and z are decremented or incremented. 16 8235b?avr?04/11 attiny20 figure 5-1. data memory map (byte addressing) 5.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 5-2 . figure 5-2. on-chip data sram access cycles 0x0000 ... 0x003f 0x0040 ... 0x00bf 0x00c0 ... 0x3eff 0x3f00 ... 0x3f01 0x3f02 ... 0x3f3f 0x3f40 ... 0x3f41 0x3f42 ... 0x3f7f 0x3f80 ... 0x3f81 0x3f82 ... 0x3fbf 0x3fc0 ... 0x3fc3 0x3fc4 ... 0x3fff 0x4000 ... 0x47ff 0x4800 ... 0xffff i/o space sram data memory (reserved) nvm lock bits (reserved) configuration bits (reserved) calibration bits (reserved) device id bits (reserved) flash program memory (reserved) clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 17 8235b?avr?04/11 attiny20 5.3 i/o memory the i/o space definition of the attiny20 is shown in ?register summary? on page 208 . all attiny20 i/os and peripherals are placed in the i/o space. all i/o locations may be accessed using the ld and st instructions, enabling data transfer between the 16 general purpose work- ing registers and the i/o space. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. see document ?avr instruction set? and section ?instruction set summary? on page 210 for more details. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note that cbi and sbi instructions will only oper ate on the specified bit, and can th erefore be used on registers contain- ing such status flags. the cbi and sbi instructions work on registers in the address range 0x00 to 0x1f, only. the i/o and peripherals control registers are explained in later sections. 18 8235b?avr?04/11 attiny20 6. clock system figure 6-1 presents the principal clock systems and their distribution in attiny20. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction reg- ister bits, as described in ?power management and sleep modes? on page 25 . the clock systems is detailed below. figure 6-1. clock distribution 6.1 clock subsystems the clock subsystems are detailed in the sections below. 6.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the syst em concerned with operat ion of the avr core. examples of such modules are the general purpose register file, the system registers and the sram data memory. halting the cpu clock inhibits the core from performing general opera- tions and calculations. 6.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counter. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. 6.1.3 nvm clock - clk nvm the nvm clock controls operation of the non-volatile memory controller. the nvm clock is usu- ally active simultane ously with the cpu clock. clock control unit general i/o modules analog-to-digital converter cpu core watchdog timer reset logic clock prescaler ram clock switch nvm calibrated oscillator clk adc source clock clk i/o clk cpu clk nvm watchdog clock watchdog oscillator external clock 19 8235b?avr?04/11 attiny20 6.1.4 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 6.2 clock sources all synchronous clock signals are derived from the main clock. the device has three alternative sources for the main clock, as follows: ? calibrated internal 8 mhz oscillator (see page 19 ) ? external clock (see page 19 ) ? internal 128 khz oscillator (see page 20 ) see table 6-3 on page 22 on how to select and change the active clock source. 6.2.1 calibrated internal 8 mhz oscillator the calibrated internal oscillato r provides an approximately 8 mhz clock signal. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 20-2 on page 174 , and ?internal oscillator speed? on page 205 for more details. this clock may be selected as the main clock by setting the clock main select bits clkms[1:0] in clkmsr to 0b00. once enabled, the oscilla tor will operate with no ex ternal components. dur- ing reset, hardware loads the calibration byte into the osccal register and thereby automatically calibrates the oscilla tor. the accuracy of this calibra tion is shown as factory cali- bration in table 20-2 on page 174 . when this oscillator is used as the main clock, the watchdog os cillator will still be used for the watchdog timer and reset time-out. for more information on the pre-programmed calibration value, see section ?calibration section? on page 166 . 6.2.2 external clock to use the device with an external clock so urce, clki should be driven as shown in figure 6-2 . the external clock is selected as the main clock by setting clkms[1:0] bits in clkmsr to 0b10. figure 6-2. external clock drive configuration when applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to en sure that the mcu is kept in reset during such changes in the clock frequency. external clock signal clki gnd 20 8235b?avr?04/11 attiny20 6.2.3 internal 128 khz oscillator the internal 128 khz oscillator is a low power oscillator providing a clock of 128 khz. the fre- quency depends on supply voltage, temperature and batch variations. this clock may be select as the main clock by setting the clkms[1:0] bits in clkmsr to 0b01. 6.2.4 switching clock source the main clock source can be switched at run-time using the ?clkmsr ? clock main settings register? on page 22 . when switching between any clock sources, the clock system ensures that no glitch occurs in the main clock. 6.2.5 default clock source the calibrated internal 8 mhz oscillator is always selected as main clock when the device is powered up or has been reset. the synchronous system clock is the main clock divided by 8, controlled by the system clock pres caler. the clock prescaler select bits can be written later to change the system clock frequency. see ?system clock prescaler?. 6.3 system clock prescaler the system clock is derived from the main clock via the system clock prescaler. the system clock can be divided by setting the ?clkpsr ? clock prescale register? on page 22 . the sys- tem clock prescaler can be used to decrease pow er consumption at times when requirements for processing power is low or to bring the system clock within limits of maximum frequency. the prescaler can be used with all ma in clock source options, and it will affect the cl ock frequency of the cpu and all synchronous peripherals. the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensur ing stable operation. 6.3.1 switching prescaler setting when switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system clock and that no interme diate frequency is higher than neither the clock frequency corresponding the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than the cpu's clock frequency. henc e, it is not possible to determine the state of the prescaler - even if it were readable, and the ex act time it takes to switch from one clock divi- sion to another cannot be exactly predicted. from the time the clkps values ar e written, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval, two active clock edges are produced. here, t1 is the previous clock period, and t2 is the perio d corresponding to the new prescaler setting. 6.4 starting 6.4.1 starting from reset the internal reset is immediately asserted when a reset source goes active. the internal reset is kept asserted until the reset source is released and the start-up sequence is completed. the start-up sequence includes three steps, as follows. 1. the first step after the reset source has bee n released consists of the device counting the reset start-up time. the purpose of this reset start-up time is to ensure that supply 21 8235b?avr?04/11 attiny20 voltage has reached sufficient levels. the reset start-up time is counted using the inter- nal 128 khz oscillator. see table 6-1 for details of reset start-up time. note that the actual supply voltage is not monitored by the start-up logic. the device will count until the reset start-up time has elap sed even if the device has reached suffi- cient supply voltage levels earlier. 2. the second step is to count the oscillator start-up time, which ensures that the cali- brated internal oscillator has r eached a stable state before it is used by the other parts of the system. the calibrated internal osc illator needs to oscilla te for a minimum num- ber of cycles before it can be considered stable. see table 6-1 for details of the oscillator start-up time. 3. the last step before releasing the internal reset is to load the calibration and the config- uration values from the non-volatile memory to configure the device properly. the configuration time is listed in table 6-1 . notes: 1. after powering up the device or after a reset the system clock is automa tically set to calibrated internal 8 mhz oscillator, divided by 8 2. when the brown-out detection is enabled, the reset start-up time is 128 ms after powering up the device. 6.4.2 starting from power-down mode when waking up from power-down sleep mode, the supply voltage is assumed to be at a suffi- cient level and only the o scillator start-up time is counted to ensu re the stable op eration of the oscillator. the oscillator start-up time is counted on the selected main clock, and the start-up time depends on the clock selected. see table 6-2 for details. notes: 1. the start-up time is measured in main clock oscillator cycles. 2. when using software bod disable, the wake-u p time from sleep mode will be approximately 60 s. 6.4.3 starting from idle / adc noise reduction / standby mode when waking up from idle, adc noise reduction or standby mode, the oscillator is already run- ning and no oscillator start-up time is introduced. table 6-1. start-up times when using the internal calibrated oscillator reset oscillator configurat ion total start-up time 64 ms 6 cycles 21 cycles 64 ms + 6 oscillat or cycles + 21 system clock cycles (1)(2) table 6-2. start-up time from power-down sleep mode. oscillator star t-up time total start-up time 6 cycles 6 oscillator cycles (1)(2) 22 8235b?avr?04/11 attiny20 6.5 register description 6.5.1 clkmsr ? clock main settings register ? bits 7:2 ? res: reserved bits these bits are reserved and will always read as zero. ? bits 1:0 ? clkms[1:0]: clock main select bits these bits select the main clock source of the system. the bits can be written at run-time to switch the source of the main clock. the clock system ensures glitch fr ee switching of the main clock source. the main clock alternatives are shown in table 6-3 . to avoid unintentional switching of main clock source, a protected change sequence must be followed to change the clkms bits, as follows: 1. write the signature for change enable of protected i/o register to register ccp 2. within four instruction cycles, write the clkms bits with the desired value 6.5.2 clkpsr ? clock prescale register ? bits 7:4 ? res: reserved bits these bits are reserved and will always read as zero. ? bits 3:0 ? clkps[3:0]: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written at run-time to vary the clock frequency and suit the application bit 765432 1 0 0x37 ? ? ? ? ? ? clkms1 clkms0 clkmsr read/writerrrrrrr/wr/w initial value 0 0 0 0 0 0 0 0 table 6-3. selection of main clock clkm1 clkm0 main clock source 0 0 calibrated internal 8 mhz oscillator 0 1 internal 128 khz osci llator (wdt oscillator) 1 0 external clock 11reserved bit 76543210 0x36 ? ? ? ? clkps3 clkps2 clkps1 clkps0 clkpsr read/write r r r r r/w r/w r/w r/w initial value00000011 23 8235b?avr?04/11 attiny20 requirements. as the prescaler divides the master clock input to the mcu, the speed of all syn- chronous peripherals is reduced accordi ngly. the division factors are given in table 6-4 . to avoid unintentional changes of clock frequency, a protected change sequence must be fol- lowed to change the clkps bits: 1. write the signature for change enable of protected i/o register to register ccp 2. within four instruction cycles, write the desired value to clkps bits at start-up, the clkps bits will be reset to 0b0011 to select the clock division factor of 8. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. 6.5.3 osccal ? oscillato r calibration register . ? bits 7:0 ? cal[7:0]: oscillator calibration value the oscillator calibration register is used to trim the calibrated in ternal oscillator and remove pro- cess variations from the oscillator fr equency. a pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in table 20-2, ?calibration accuracy of internal rc oscillator,? on page 174 . table 6-4. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0 0 1 1 8 (default) 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved bit 76543210 0x39 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 24 8235b?avr?04/11 attiny20 the application software can write this register to cha nge the oscillator fre quency. the oscillator can be calibrated to frequencies as specified in table 20-2, ?calibration accuracy of internal rc oscillator,? on page 174 . calibration outside the range given is not guaranteed. the cal[7:0] bits are used to tu ne the frequency of the oscillator. a setting of 0x00 gives the lowest frequency, and a setting of 0xff gives the highest frequency. 25 8235b?avr?04/11 attiny20 7. power management and sleep modes the high performance and industry leading code efficiency makes the avr microcontrollers an ideal choise for low power applications. in addition, sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. 7.1 sleep modes figure 6-1 on page 18 presents the different clock systems and their distribution in attiny20. the figure is helpful in selecting an appropriate sleep mode. table 7-1 shows the different sleep modes and their wake up sources. notes: 1. for int0, only level interrupt. 2. only twi address match interrupt. to enter any of the four sleep modes, the se bits in mcucr must be written to logic one and a sleep instruction must be executed. the sm[2:0] bits in the mcucr register select which sleep mode (idle, adc noise reduction, standby or power-down) will be activated by the sleep instruct ion. see table 7-2 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the st art-up time, executes the interrupt routine, and resumes execution from the instruction followi ng sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the mcu (and for the mcu to enter the interrupt service routine). see ?external interrupts? on page 39 for details. 7.1.1 idle mode when bits sm[2:0] are written to 000, the sleep instructio n makes the mcu enter idle mode, stopping the cpu but allowing the analog comparator, adc, timer/counters, watchdog, twi, spi and the interrupt system to continue oper ating. this sleep mode basically halts clk cpu and clk nvm , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow. if wake-up from the analog comparator interrupt is not required, the table 7-1. active clock domains and wake-up sources in different sleep modes. sleep mode active clock domains osci llators wake-up sources clk cpu clk nvm clk io clk adc main clock source enabled int0 and pin change watchdog interrupt twi slave adc other i/o idle xx x xxxxx adc noise reduction x x x (1) xx (2) x standby x x (1) xx (2) power-down x (1) xx (2) 26 8235b?avr?04/11 attiny20 analog comparator can be powered down by setting the acd bit in ?acsra ? analog compara- tor control and status register? on page 109 . this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. 7.1.2 adc noise reduction mode when bits sm[2:0] are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, twi and the watchdog to continue operating (if enabled). this sleep mode halts clk i/o , clk cpu , and clk nvm , while allowing the ot her clocks to run. this mode improves the noise environment for the adc, enabling higher resolution measure- ments. if the adc is enabled, a conversion starts automatically when this mode is entered. 7.1.3 power-down mode when bits sm[2:0] are written to 010, the sleep instruction makes the mcu enter power-down mode. in this mode, the oscillator is stopped, while the external interrupts, twi and the watch- dog continue operating (if enabled). only a watchdog reset, an external level interrupt on int0, a pin change interrupt, or a twi slave interrupt can wake up the mcu. this sleep mode halts all generated clocks, allowing operation of asynchronous modules only. 7.1.4 standby mode when bits sm[2:0] are written to 100, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept run- ning. this reduces wake-up time, because the oscillator is already running and doesn't need to be started up. 7.2 software bod disable when the brown-out detector (bod) is enabled by bodlevel fuses (see table 19-5 on page 165 ), the bod is actively monitoring the supply vo ltage during a sleep period. in some devices it is possible to save power by disabling the bod by software in power-down and stand-by sleep modes. the sleep mode power consum ption will then be at the same level as when bod is glob- ally disabled by fuses. if bod is disabled by software, the bod function is turned off immediately after entering the sleep mode. upon wake-up from sleep, bod is automatically enabled again. this ensures safe operation in case the v cc level has dropped during the sleep period. when the bod has been disabled, the wake-up time from sleep mode will be approximately 60s to ensure that the bod is working corr ectly before the mcu continues executing code. bod disable is controlled by the bods (bod sleep) bit of mcu control register, see ?mcucr ? mcu control register? on page 28 . writing this bit to one turns off bod in power-down and stand-by, while writing a zero keeps the bod active . the default setting is zero, i.e. bod active. writing to the bods bit is controlled by a timed sequence, see ?mcucr ? mcu control regis- ter? on page 28 . 27 8235b?avr?04/11 attiny20 7.3 power reduction register the power reduction register (prr), see ?prr ? power reduction register? on page 29 , pro- vides a method to reduce power consumption by stopping the clock to individual peripherals. when the clock for a peripheral is stopped then: ? the current state of the peripheral is frozen. ? the associated registers can not be read or written. ? resources used by the perip heral will remain occupied. the peripheral should in most cases be disabled before stopping the clock. clearing the prr bit wakes up the peripheral and puts it in the same state as before shutdown. peripheral shutdown can be used in idle mode an d active mode to significantly reduce the over- all power consumption. see ?supply current of i/o modules? on page 179 for examples. in all other sleep modes, the clock is already stopped. 7.4 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr core controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operat- ing. all functions not needed shoul d be disabled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 7.4.1 analog comparator when entering idle mode, the analog comparator should be disabled if not used. in the power- down mode, the analog comparator is automatically disabled. see ?analog comparator? on page 108 for further details. 7.4.2 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. see ?analog to digital converter? on page 112 for details on adc operation. 7.4.3 watchdog timer if the watchdog timer is not needed in the application, this module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?watchdog timer? on page 33 for details on how to configure the watchdog timer. 7.4.4 brown-out detector if the brown-out detector is not needed in the application, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. see ?brown-out detection? on page 32 and ?software bod dis- able? on page 26 for details on how to configure the brown-out detector. 28 8235b?avr?04/11 attiny20 7.4.5 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important thing is then to ensure that no pins drive resistive loads. in sleep modes where the i/o clock (clk i/o ) is stopped, the input bu ffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up co nditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 48 for details on which pins are enabled. if the input buffer is enabled and the input signal is left fl oating or has an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable register (didr0). refer to ?didr0 ? digital input disable register 0? on page 111 for details. 7.5 register description 7.5.1 mcucr ? mcu control register the mcu control register contains bits for controlling ex ternal interrupt sensing and power management. ? bit 5 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 4 ? bods: bod sleep in order to disable bod during sleep (see table 7-1 on page 25 ) the bods bit must be written to logic one. this is controlled by a protected change sequence, as follows: 1. write the signature for change enable of protected i/o registers to register ccp. 2. within four instruction cycles write the bods bit. a sleep instruction must be execut ed while bods is active in or der to turn off the bod for the actual sleep mode. the bods bit is automatically cleared when the device wakes up. alternatively the bods bit can be cleared by writing logic zero to it. this does not require protected sequence. ? bits 3:1 ? sm[2:0]: sleep mode select bits 2 - 0 these bits select between available sleep modes, as shown in table 7-2 . bit 76543210 0x3a isc01 isc00 ? bods sm2 sm1 sm0 se mcucr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 7-2. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010power-down 29 8235b?avr?04/11 attiny20 ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu enteri ng the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. 7.5.2 prr ? power reduction register ? bits 7:5 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 4 ? prtwi: power reduction two-wire interface writing a logic one to this bit shuts down the two-wire interface module. ? bit 3 ? prspi: power reduction serial peripheral interface writing a logic one to this bit shuts down the serial peripheral interface module. ? bit 2 ? prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabled, operation will cont inue like before the shutdown. ? bit 1 ? prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, operation will cont inue like before the shutdown. ? bit 0 ? pradc: power reduction adc writing a logic one to this bit shuts down the adc. the adc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. 011reserved 100standby 101reserved 110reserved 111reserved table 7-2. sleep mode select (continued) sm2 sm1 sm0 sleep mode bit 7 6 5 4 3 2 1 0 0x35 ? ? ? prtwi prspi prtim1 prtim0 pradc prr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 30 8235b?avr?04/11 attiny20 8. system control and reset 8.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 8-1 shows the reset logic. electrical pa rameters of the reset circuitry are defined in section ?system and reset characteristics? on page 175 . figure 8-1. reset logic the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the start up sequence is described in ?starting from reset? on page 20 . 8.2 reset sources the attiny20 has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ) ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled ? brown out reset. the mcu is reset when the brown-out detector is enabled and supply voltage is below the brown-out threshold (v bot ) 8.2.1 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in section ?system and reset characteristics? on page 175 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the data b u s reset flag register r e s e t f l a g r e g i s t e r (rstflr) ( r s t f l r ) power-on p o w e r - o n reset circuit r e s e t c i r c u i t pull-up p u l l - u p resistor r e s i s t o r bodlevel2...0 b o d l e v e l 2 . . . 0 v cc c c spike s p i k e filter f i l t e r reset r e s e t external e x t e r n a l reset circuit r e s e t c i r c u i t brown out b r o w n o u t reset circuit r e s e t c i r c u i t rstdisbl r s t d i s b l watchdog w a t c h d o g timer t i m e r delay d e l a y counters c o u n t e r s s r q watchdog w a t c h d o g oscillator o s c i l l a t o r clock c l o c k generator g e n e r a t o r borf porf extrf wdrf internal i n t e r n a l reset r e s e t ck c k timeout t i m e o u t counter re s et c o u n t e r r e s e t 31 8235b?avr?04/11 attiny20 device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. figure 8-2. mcu start-up, reset tied to v cc figure 8-3. mcu start-up, reset extended externally 8.2.2 external reset an external reset is generated by a low level on the reset pin if enabled. reset pulses longer than the minimum pulse width (see section ?system and reset characteristics? on page 175 ) will generate a reset, even if th e clock is not running. shorter pulses are not g uaranteed to gen- erate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. external reset is ignored during power-on start-up count. after power-on reset the internal reset is extended only if reset pin is low when the initial power-on delay co unt is complete. see fig- ure 8-2 and figure 8-3 . v time-out reset reset tout internal t v pot v rst cc v t ime-out tout tout internal cc t v pot v rst > t reset reset 32 8235b?avr?04/11 attiny20 figure 8-4. external reset during operation 8.2.3 watchdog reset when the watchdog times out, it will generate a short reset puls e. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . see page 32 for details on oper- ation of the watchdog timer and table 20-4 on page 175 for details on reset time-out. figure 8-5. watchdog reset during operation 8.2.4 brown-out detection attiny20 has an on-chip brown-out detect ion (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trig ger level has a hysteresis to ensure spike fr ee brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 8-6 on page 33 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 8-6 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for lon- ger than t bod given in ?system and reset characteristics? on page 175 . cc ck cc 33 8235b?avr?04/11 attiny20 figure 8-6. brown-out reset during operation 8.3 internal voltage reference attiny20 features an internal bandgap reference. this reference is used for brown-out detec- tion, and it can be used as an input to the analog comparator or the adc. the bandgap voltage varies with supply voltage and temperature. 8.3.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in ?system and reset characteristics? on page 175 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by pr ogramming the bodlevel[2:0] fuse). 2. when the internal reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 8.4 watchdog timer the watchdog timer is clocked from an on-c hip oscillator, which runs at 128 khz. see figure 8- 7 on page 34 . by controlling the watchdog timer presca ler, the watchdog reset interval can be adjusted as shown in table 8-2 on page 36 . the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also re set when it is disabled and when a device reset occurs. ten different cloc k cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the attiny20 resets and executes from the reset vector. for timing details on the watchdog reset, refer to table 8-3 on page 36 . v cc reset time-out internal reset v bot- v bot+ t tout 34 8235b?avr?04/11 attiny20 figure 8-7. watchdog timer the wathdog timer can also be configured to generate an interrupt instead of a reset. this can be very helpful when using the watchdog to wake-up from power-down. to prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse wdton as shown in table 8-1 on page 34 . see ?procedure for changing the watchdog timer configuration? on page 34 for details. 8.4.1 procedure for changing the watchdog timer configuration the sequence for changing configuration differs between the two safety levels, as follows: 8.4.1.1 safety level 1 in this mode, the watchdog time r is initially disabled, but can be enabled by writing the wde bit to one without any restriction. a special sequence is needed when disabling an enabled watch- dog timer. to disable an enabled watchdog timer, the following procedure must be followed: 1. write the signature for change enable of protected i/o registers to register ccp 2. within four instruction cycles, in the same operation, write wde and wdp bits 8.4.1.2 safety level 2 in this mode, the watchdog time r is always enabled, and the wde bit will always read as one. a protected change is needed when changing the watchdog time-out period. to change the watchdog time-out, the following procedure must be followed: 1. write the signature for change enable of protected i/o registers to register ccp 2. within four instruction cycles, write the wd p bit. the value written to wde is irrelevant table 8-1. wdt configuration as a function of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled protected change sequence no limitations programmed 2 enabled always enabled protected change sequence osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k mcu reset watchdog prescaler 128 khz oscillator watchdog reset wdp0 wdp1 wdp2 wdp3 wde mux 35 8235b?avr?04/11 attiny20 8.4.2 code examples the following code example shows how to turn off the wdt. the example assumes that inter- rupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. note: see ?code examples? on page 6 . 8.5 register description 8.5.1 wdtcsr ? watchdog timer control and status register ? bit 7 ? wdif: watchdog timer interrupt flag this bit is set when a time-out occurs in the watchdog timer and the watchdog timer is config- ured for interrupt. wdif is cleared by hardw are when executing the corresponding interrupt handling vector. alternatively, wdif is cleared by writing a logic one to the flag. when the wdie is set, the watchdog time-out interrupt is requested. ? bit 6 ? wdie: watchdog timer interrupt enable when this bit is written to one, the watchdog interrupt request is enabled. if wde is cleared in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is requested if time-out in the watchdog timer occurs. if wde is set, the watchdog timer is in interrupt and system reset mode. the first time-out in the watchdog timer will set wdif. executing t he corresponding interrup t vector will clear wdie and wdif automatically by hardware (the watchd og goes to system reset mode). this is use- ful for keeping the watchdog timer security while using the interrupt. to stay in interrupt and system reset mode, wdie must be set after each interrupt. this should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the assembly code example wdt_off: wdr ; clear wdrf in rstflr in r16, rstflr andi r16, ~(1< 37 8235b?avr?04/11 attiny20 8.5.2 rstflr ? reset flag register the reset flag register provides information on which reset source caused an mcu reset. ? bits 7:4 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog re set occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the rstflr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 1010 reserved 1011 1100 1101 1110 1111 table 8-3. watchdog timer prescale select (continued) wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v bit 76543210 0x3b ? ? ? ? wdrf borf extrf porf rstflr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 x x x x 38 8235b?avr?04/11 attiny20 9. interrupts this section describes the specifics of the interrupt handling as performed in attiny20. for a general explanation of the avr interrupt handling, see ?reset and interrupt handling? on page 11 . 9.1 interrupt vectors the interrupt vectors of attiny20 are described in table 9-1 below. in case the program never enab les an interrupt source, the interrupt vectors will not be used and, consequently, regular program code can be placed at these locations. table 9-1. reset and interrupt vectors vector no. program address label interrupt source 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset 2 0x0001 int0 external interrupt request 0 3 0x0002 pcint0 pin change interrupt request 0 4 0x0003 pcint1 pin change interrupt request 1 5 0x0004 wdt watchdog time-out 6 0x0005 tim1_capt timer/counter1 input capture 7 0x0006 tim1_compa timer/counter1 compare match a 8 0x0007 tim1_compb timer/counter1 compare match b 9 0x0008 tim1_ovf timer/counter1 overflow 10 0x0009 tim0_compa timer/counter0 compare match a 11 0x000a tim0_compb timer/counter0 compare match b 12 0x000b tim0_ovf timer/counter0 overflow 13 0x000c ana_comp analog comparator 14 0x000d adc adc conversion complete 15 0x000e twi_slave two-wire interface 16 0x000f spi serial peripheral interface 17 0x0010 qtrip (1) 1. the touch sensing interrupt source is related to the qtouch library support. touch sensing 39 8235b?avr?04/11 attiny20 a typical and general setup for interrupt vector addresses in attiny20 is shown in the program example below. note: see ?code examples? on page 6 . 9.2 external interrupts external interrupts are triggered by the int0 pi n or any of the pcint[11:0] pins. observe that, if enabled, the interrupts will trigger even if the int0 or pcint[11:0] pins are configured as out- puts. this feature provides a way of generating a software interrupt. pin change 0 interrupts pci0 will trigger if any enabled pc int[7:0] pin toggles. pin change 1 interrupts pci1 will trigger if any enabled pc int[11:8] pin toggles. the pcmsk0 and pcmsk1 registers control which pins contribute to the pin change interrupts. pin change interrupts on pcint[11:0] are detected asynchronously, which means that these interrupts can be used for waking the part also from sleep modes other than idle mode. the int0 interrupt can be triggered by a falling or rising edge or a low level. this is set up as shown in ?mcucr ? mcu control register? on page 41 . when the int0 interrupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int0 requires the presence of an i/o clock, as described in ?clock system? on page 18 . assembly code example .org 0x0000 ;set address of next statement rjmp reset ; address 0x0000 rjmp int0_isr ; address 0x0001 rjmp pcint0_isr ; address 0x0002 rjmp pcint1_isr ; address 0x0003 rjmp wdt_isr ; address 0x0004 rjmp tim1_capt_isr ; address 0x0005 rjmp tim1_compa_isr ; address 0x0006 rjmp tim1_compb_isr ; address 0x0007 rjmp tim1_ovf_isr ; address 0x0008 rjmp tim0_compa_isr ; address 0x0009 rjmp tim0_compb_isr ; address 0x000a rjmp tim0_ovf_isr ; address 0x000b rjmp ana_comp_isr ; address 0x000c rjmp adc_isr ; address 0x000d rjmp twi_slave_isr ; address 0x000e rjmp spi_isr ; address 0x000f rjmp qtrip_isr ; address 0x0010 reset: ; main program start 40 8235b?avr?04/11 attiny20 9.2.1 low level interrupt a low level interrupt on int0 is detected asyn chronously. this means that the interrupt source can be used for waking the part also from sleep modes other than idle (the i/o clock is halted in all sleep modes except idle). note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. th e start-up time is defined as described in ?clock system? on page 18 . if the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service ro utine but continue from the instruction fol- lowing the sleep command. 9.2.2 pin change interrupt timing a timing example of a pin change interrupt is shown in figure 9-1 . figure 9-1. timing of pin change interrupts clk pcint(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag pcif pcint(0) pin_sync pcint_syn pin_lat d q le pcint_setflag pcif clk clk pcint(0) in pcmsk(x) pcint_in_(0) 0 x 41 8235b?avr?04/11 attiny20 9.3 register description 9.3.1 mcucr ? mcu control register the mcu control register contains bits for controlling ex ternal interrupt sensing and power management. ? bits 7:6 ? isc01, isc00: interrupt sense control the external interrupt 0 is activated by the exte rnal pin int0 if the sreg i-flag and the corre- sponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 9-2 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. 9.3.2 gimsk ? general interrupt mask register ? bits 7:6 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 5 ? pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. an y change on any enabled pcint[ 11:8] pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint[11:8] pins are enabled individually by the pcmsk1 register. ? bit 4 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint[7:0] pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint[7:0] pins are enabled individually by the pcmsk0 register. bit 76543210 0x3a isc01 isc00 ? bods sm2 sm1 sm0 se mcucr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 9-2. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. bit 76543210 0x0c ? ? pcie1 pcie0 ? ? ? int0 gimsk read/write r r r/w r/w r r r r/w initial value 0 0 0 0 0 0 0 0 42 8235b?avr?04/11 attiny20 ? bits 3:1 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 0 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control bits (isc01 and isc00) in the mcu control register (mcucr) define whether the external interrupt is activated on rising and/or fall- ing edge of the int0 pin or level sensed. activi ty on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from the int0 interrupt vector. 9.3.3 gifr ? general interrupt flag register ? bits 7:6 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 5 ? pcif1: pin change interrupt flag 1 when a logic change on any pcint[11:8] pin triggers an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in gimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. ? bit 4 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint[7:0] pin triggers an interrupt request, pcif becomes set (one). if the i-bit in sreg and the pcie0 bit in gimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. ? bits 3:1 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (o ne), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. bit 76543210 0x0b ? ? pcif1 pcif0 ? ? ? intf0 gifr read/write r r r/w r/w r r r r/w initial value 0 0 0 0 0 0 0 0 43 8235b?avr?04/11 attiny20 9.3.4 pcmsk1 ? pin change mask register 1 ? bits 7:4 ? res: reserved bits these bits are reserved and will always read as zero. ? bits 3:0 ? pcint[11:8] : pin change enable mask 11:8 each pcint[11:8] bit selects whether pin c hange interrupt is enabled on the corresponding i/o pin. if pcint[11:8] is set and the pcie1 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint[11:8] is cleared, pin change interrupt on the corresponding i/o pin is disabled. 9.3.5 pcmsk0 ? pin change mask register 0 ? bits 7:0 ? pcint[7:0] : pin change enable mask 7:0 each pcint[7:0] bit selects whether pin c hange interrupt is enabled on the corresponding i/o pin. if pcint[7:0] is set and the pcie0 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint[7:0] is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 7 6 5 4 3 2 1 0 0x0a ? ? ? ? pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x09 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 44 8235b?avr?04/11 attiny20 10. i/o ports 10.1 overview all avr ports have true read-modi fy-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when chang- ing drive value (if configured as output) or enab ling/disabling of pull-up resistors. each output buffer has symmetrical drive char acteristics with both high sink and source capability. the pin driver is strong enough to drive led displays directly. all port pins have individually selectable pull-up resistors with a supply-voltage invariant re sistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 10-1 on page 44 . see ?electrical characteristics? on page 172 for a complete list of parameters. figure 10-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a progr am, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o regis- ters and bit locations are listed in ?register description? on page 58 . four i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, pull -up enable register ? puex, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register, the data direction register, and the pull-up enable register are read/write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the corresponding bit in the data register. using the i/o port as general digital i/o is described in ?ports as general digital i/o? on page 45 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 49 . refer to the individual module sectio ns for a full description of the alter- nate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu see figure "general digital i/o" for details pxn 45 8235b?avr?04/11 attiny20 10.2 ports as gener al digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 10-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 10-2. general digital i/o (1) note: 1. wex, wrx, wpx, wdx, rex, rrx, rpx, a nd rdx are common to all pins within the same port. clk i/o , and sleep are common to all ports. 10.2.1 configuring the pin each port pin consists of four register bits : ddxn, portxn, puexn, and pinxn. as shown in ?register description? on page 58 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, the puexn bits at the puex i/o address, and the pinxn bits at the pinx i/o address. clk rpx rrx rdx wdx wex synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin clk i/o : i/o clock rdx: read ddrx wex: write puex rex: read puex d l q q rex reset reset q q d q qd clr portxn q qd clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o wpx reset q qd clr puexn 0 1 wrx wpx: write pinx register 46 8235b?avr?04/11 attiny20 the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). the pull-up resistor is activated, if the puexn is written logic one. to switch the pull-up resistor off, puexn has to be written logic zero. table 10-1 summarizes the control signals for the pin value. port pins are tri-stated when a reset cond ition becomes active, even when no clocks are running. 10.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 10.2.3 break-before-make switching in break-before-make mode, switching the ddrxn bit from input to output introduces an imme- diate tri-state period lasting one s ystem clock cycle, as indicated in figure 10-3 . for example, if the system clock is 4 mhz and the ddrxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of portxn is seen on the port pin. to avoid glitches it is re commended that the maximum ddrxn toggle frequency is two system clock cycles. the break-before-make mode applies to the entire port and it is activated by the bbmx bit. for more details, see ?portcr ? port control register? on page 58 . when switching the ddrxn bit from output to input no immediate tr i-state period is introduced. table 10-1. port pin configurations ddxn portxn puexn i/o pull-up comment 0x 0 input no tri-state (hi-z) 0x 1 input yes sources current if pulled low externally 10 0 output no output low (sink) 10 1 output yes not recommended. output low (sink) and internal pull-up active. sources current through the internal pull-up resistor and consumes power constantly 11 0 output no output high (source) 11 1 output yes output high (source) and internal pull-up active 47 8235b?avr?04/11 attiny20 figure 10-3. switching between input and output in break-before-make-mode 10.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 10-2 on page 45 , the pinxn register bit and the preced- ing latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 10-4 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 10-4. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd,max and tpd,min, a single signal tr ansition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. out ddrx, r16 nop 0x02 0x01 system clk instructions ddrx intermediate tri-state cycle out ddrx, r17 0x55 portx 0x01 intermediate tri-state cycle px0 px1 tri-state tri-state tri-state 0x01 r17 0x02 r16 xxx in r17, pinx 0x00 0xff in s truction s s ync latch pinxn r17 xxx s y s tem clk t pd, m a x t pd, min 48 8235b?avr?04/11 attiny20 when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 10-5 on page 48 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is one system clock period. figure 10-5. synchronization when reading a software assigned pin value 10.2.5 digital input enable and sleep modes as shown in figure 10-2 on page 45 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. th e signal denoted sleep in the fi gure, is set by the mcu sleep controller in power-down and standby modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pins. sl eep is also overri dden by various other alternate functions as described in ?alternate port functions? on page 49 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.2.6 unconnected pins if some pins are unused, it is recommended to ens ure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (reset, active mode and idle mode). the simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. in this case, the pull-up will be disabled during reset. if low po wer consumption during reset is important, it is recommended to use an external pull-up or pulldown. connecting unused pins directly to v cc or gnd is not recommended, since this ma y cause excessive curr ents if the pin is accidentally configured as an output. out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 49 8235b?avr?04/11 attiny20 10.2.7 program example the following code example shows how to set port b pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: see ?code examples? on page 6 . 10.3 alternate port functions most port pins have alternate functions in addition to being general digital i/os. in figure 10-6 below is shown how the port pin control signals from the simplified figure 10-2 on page 45 can be overridden by alternate functions. assembly code example ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 51 8235b?avr?04/11 attiny20 table 10-2 on page 51 summarizes the function of the overriding signals. the pin and port indexes from figure 10-6 on page 50 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 10-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-u p enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when puexn = 0b1. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the puexn register bit. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output dr iver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital in put enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to altern ate functions. in the figure, the signal is connected to the out put of the schmitt-trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 52 8235b?avr?04/11 attiny20 10.3.1 alternate functions of port a the port a pins with alternate function are shown in table 10-3 . ? port a, bit 0 ? adc0/pcint0 ? adc0: analog to digital converter, channel 0 . ? pcint0: pin change interrupt source 0. the pa0 pin can serve as an external interrupt source for pin change interrupt 0. ? port a, bit 1 ? adc1/ain0/pcint1 ? adc1: analog to digital converter, channel 1 . ? ain0: analog comparator positive input. configure the port pin as input with the internal pull- up switched off to avoid the digital port function from interfering with the function of the analog comparator. ? pcint1: pin change interrupt source 1. the pa1 pin can serve as an external interrupt source for pin change interrupt 0. table 10-3. port a pins alternate functions port pin alternate function pa 0 adc0: adc input channel 0 pcint0: pin change interrupt 0, source 0 pa 1 adc1: adc input channel 1 ain0: analog comparator, positive input pcint1:pin change interrupt 0, source 1 pa 2 adc2: adc input channel 2 ain1: analog comparator, negative input pcint2: pin change interrupt 0, source 2 pa 3 adc3: adc input channel 3 pcint3: pin change interrupt 0, source 3 pa 4 adc4: adc input channel 4 pcint4: pin change interrupt 0, source 4 pa 5 adc5: adc input channel 5 pcint5: pin change interrupt 0, source 5 pa 6 adc6: adc input channel 6 ss : spi slave select pcint6: pin change interrupt 0, source 6 pa 7 adc7: adc input channel 7 oc0b:: timer/counter0 compare match b output icp1: timer/counter1 input capture pin t1: timer/counter1 clock source scl: twi clock sck: spi clock pcint7: pin change interrupt 0, source 7 53 8235b?avr?04/11 attiny20 ? port a, bit 2 ? adc2/ain1/pcint2 ? adc2: analog to digital converter, channel 2 . ? ain1: analog comparator negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. ? pcint2: pin change interrupt source 2. the pa2 pin can serve as an external interrupt source for pin change interrupt 0. ? port a, bit 3 ? adc3/pcint3 ? adc3: analog to digital converter, channel 3 . ? pcint3: pin change interrupt source 3. the pa3 pin can serve as an external interrupt source for pin change interrupt 0. ? port a, bit 4 ? adc4/pcint4 ? adc4: analog to digital converter, channel 4 . ? pcint4: pin change interrupt source 4. the pa4 pin can serve as an external interrupt source for pin change interrupt 0. ? port a, bit 5 ? adc5/pcint5 ? adc5: analog to digital converter, channel 5 . ? pcint5: pin change interrupt source 5. the pa5 pin can serve as an external interrupt source for pin change interrupt 0. ? port a, bit 6 ? adc6/ss /pcint6 ? adc6: analog to digital converter, channel 6 . ?ss : slave select input. regardless of dda6, this pin is automatically configured as an input when spi is enabled as a slave. the data direction of this pin is controlled by dda6 when spi is enabled as a master. ? pcint6: pin change interrupt source 6. the pa6 pin can serve as an external interrupt source for pin change interrupt 0. ? port a, bit 7 ? adc7/oc0b/icp1/t1/scl/sck/pcint7 ? adc7: analog to digital converter, channel 7 . ? oc0b: output compare match output. the pa7 pin can serve as an external output for the timer/counter0 compare match b. the pin has to be configured as an output (dda7 set (one)) to serve this function. this is also the output pin for the pwm mode timer function. ? icp1: input capture pin. the pa7 pin can act as an input capture pin for timer/counter1. ? t1: timer/counter1 counter source. ? scl: twi clock. the pin is disconnected from the port and becomes the serial clock for the twi when twen in twscra is set. in this mode of operation, the pin is driven by an open drain driver with slew rate limitation and a spike filter. ? sck: spi master clock output / slave clock input. regardless of dda7, this pin is automatically configured as an input when spi is enabled as a slave. the data direction of the pin is controlled by dda7 when spi is enabled as a master. ? pcint7: pin change interrupt source 7. the pa7 pin can serve as an external interrupt source for pin change interrupt 0. 54 8235b?avr?04/11 attiny20 table 10-4 and table 10-5 relate the alternate functions of port a to the overriding signals shown in figure 10-6 on page 50 . note: when twi is enabled the slew rate control and sp ike filter are activated on pa7. this is not illus- trated in figure 10-6 on page 50 . the spike filter is connec ted between aioxn and the twi module. table 10-4. overriding signals for alternate functions in pa[7:5] signal name pa7/adc7/oc0b/icp1/ t1/scl/sck/pcint7 pa6/adc6/ss /pcint6 pa5/adc5/pcint5 puoe000 puov000 ddoe twen + (spe ? mstr ) spe ? mstr 0 ddov twen ? scl_out 00 pvoe twen + (spe ? mstr) + oc0b_enable 00 pvov twen ? (spe ? mstr ? sck_out + (spe + mstr ) ? oc0b) 00 ptoe000 dieoe pcint7 ? pcie0 + adc7d pcint6 ? pcie0 + adc6d pcint5 ? pcie0 + adc5d dieov pcint7 ? pcie0 pcint6 ? pcie0 pcint5 ? pcie0 di icp1 / sck / t1 / scl / pcint7 input spi ss / pcint6 input pcint5 input aio adc7 / scl input adc6 input adc5 input table 10-5. overriding signals for alternate functions in pa[4:2] signal name pa4/adc4/pcint4 pa3/adc3/pcint3 pa2/adc2/ain1/pcint2 puoe000 puov000 ddoe 0 0 0 ddov 0 0 0 pvoe000 pvov000 ptoe000 dieoe (pcint4 ? pcie0) + ad c4d (pcint3 ? pcie0) + adc3 d (pcint2 ? pcie0) + adc2d dieov (pcint4 ? pcie0) pcin t3 ? pcie0 pcint3 ? pcie0 di pcint4 input pcint1 input pcint0 input aio adc4 input adc3 input adc2 / analog comparator negative input 55 8235b?avr?04/11 attiny20 10.3.2 alternate functions of port b the port b pins with alternate function are shown in table 10-7 . table 10-6. overriding signals for alternate functions in pa[1:0] signal name pa1/adc1/ain0/pcint1 pa0/adc0/pcint0 puoe 0 0 puov 0 0 ddoe 0 0 ddov 0 0 pvoe 0 0 pvov 0 0 ptoe 0 0 dieoe pcint1 ? pcie0 + adc1d pcint0 ? pcie0 + adc0d dieov pcint1 ? pcie0 pcint0 ? pcie0 di pcint1 input pcint0 input aio adc1 / analog comparator positive input adc1 input table 10-7. port b pins alternate functions port pin alternate function pb0 t0: timer/counter0 clock source clki: external clock input tpiclk: serial programming clock pcint8: pin change interrupt 1, source 8 pb1 oc1a: timer/counter1 compare match a output sda: twi data input/output mosi: spi master ou tput / slave input tpidata: serial programming data pcint9: pin change interrupt 1, source 9 pb2 int0: external interrupt 0 input oc0a: timer/counter0 compare match a output oc1b: timer/counter1 compare match b output miso: spi master input / slave output ckout: system clock output pcint10:pin change interrupt 1, source 10 pb3 reset : reset pin pcint11:pin change interrupt 1, source 11. 56 8235b?avr?04/11 attiny20 ? port b, bit 0 ? t0/clki/tpiclk/pcint8 ? t0: timer/counter0 clock source. ? clki: clock input from an external clock source, see ?external clock? on page 19 . ? tpiclk: serial programming clock. ? pcint8: pin change interrupt source 8. the pb0 pin can serve as an external interrupt source for pin change interrupt 1. ? port b, bit 1 ? oc1a/sda/mosi/tpidata/pcint9 ? oc1a: output compare match output. provided that the pin has been configured as an output it serves as an external output for timer/counter1 compare match a. this pin is also the output for the timer/counter pwm mode function. ? sda: twi data. the pin is disconnected from the port and becomes the serial data for the twi when twen in twscra is set. in this mode of operation, the pin is driven by an open drain driver with slew rate limitation and a spike filter. ? mosi: spi master output / slave input. regardless of ddb1, this pin is automatically configured as an input when spi is enabled as a slave. the data direction of this pin is controlled by ddb1 when spi is enabled as a master. ? tpidata: serial programming data. ? pcint9: pin change interrupt source 9. the pb1 pin can serve as an external interrupt source for pin change interrupt 1. ? port b, bit 2 ? int0/oc0 a/oc1b/miso/ckout/pcint10 ? int0: external interrupt request 0. ? oc0a: output compare match output. provided that the pin has been configured as an output it serves as an external output for timer/counter0 compare match a. this pin is also the output for the timer/counter pwm mode function. ? oc1b: output compare match output. provided that the pin has been configured as an output it serves as an external output for timer/counter1 compare match b. this pin is also the output for the timer/counter pwm mode function. ? miso: spi master input / slave output. regardless of ddb2, this pin is automatically configured as an input when spi is enabled as a master. the data direction of this pin is controlled by ddb2 when spi is enabled as a slave. ? ckout - system clock output: the system clock can be output on the pb2 pin. the system clock will be output if the ckout fuse is prog rammed, regardless of the portb2 and ddb2 settings. it will also be output during reset. ? pcint10: pin change interrupt source 10. the pb2 pin can serve as an external interrupt source for pin change interrupt 1. ? port b, bit 3 ? reset /pcint11 ? reset : external reset input is active low and enabled by unprogramming (?1?) the rstdisbl fuse. pullup is activated and output driver and digital input are deactivated when the pin is used as the reset pin. ? pcint11: pin change interrupt source 11. the pb3 pin can serve as an external interrupt source for pin change interrupt 1. 57 8235b?avr?04/11 attiny20 table 10-8 on page 57 and table 10-9 on page 57 relate the alternate functions of port b to the overriding signals shown in figure 10-6 on page 50 . note: when twi is enabled the slew rate control and spike filter are activate on pb1. this is not illus- trated in figure 10-6 on page 50 . the spike filter is connec ted between aioxn and the twi. table 10-8. overriding signals for alternate functions in pb[3:2] signal pb3/ reset / pcint11 pb2/int0/oc0a/oc1b/miso/ckout/pcint10 puoe rstdisbl (1) 1. rstdisbl is 1 when the configuration bit is ?0? (programmed) ckout (2) 2. ckout is 1 when the configuration bit is ?0? (programmed) puov 1 0 ddoe rstdisbl (1) ckout (2) + (spe ? mstr) ddov 0 ckout (2) pvoe rstdisbl (1) ckout + oc0a_enabl e + oc1b_enable + (spe ? mstr ) pvov 0 ckout (2) ? system clock + ckout ? spe ? mstr ? spi_slave_out + ckout ? (spe + mstr) ? oc1b_enable ? oc1b + ckout ? (spe + mstr) ? oc1b_enable ? oc0a ptoe 0 0 dieoe rstdisbl (1) + (pcint11 ? pcie1) (pcint10 ? pcie1) + int0 dieov rstdisbl (1) ? pcint11 ? pcie1 (pcint10 ? pcie1) + int0 di pcint11 input int0 / pcint10 / spi master input aio table 10-9. overriding signals for alternate functions in pb[1:0] signal pb1/oc1a/sda/mosi/pcint9 pb0/t0/clki/pcint8 puoe 0 ext_clock (1) 1. ext_clock = external clock is selected as system clock. puov 0 0 ddoe (spe ? mstr ) + twen ext_clock (1) ddov twen ? sda_out 0 pvoe twen + (spe ? mstr) + oc1a_enable ext_clock (1) pvov twen ? spe ? mstr ? spi_master_out + twen ? (spe + mstr ) ? oc1a 0 ptoe 0 0 dieoe pcint9 ? pcie1 ext_clock (1) + (pcint8 ? pcie1) dieov pcint9 ? pcie1 ( ext_clock (1) ? pwr_down ) + (ext_clock (1) ? pcint8 ? pcie1) di pcint9 / spi slave input clock / pcint8 / t0 input aio sda input 58 8235b?avr?04/11 attiny20 10.4 register description 10.4.1 portcr ? port control register ? bits 7:2 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 1 ? bbmb: break-before-make mode enable when this bit is set the break-before-make mode is activated for the entire port b. the interme- diate tri-state cycle is then inserted when writing ddrbn to make an output. for further information, see ?break-before-make switching? on page 46 . ? bit 0 ? bbma: break-before-make mode enable when this bit is set the break-before-make mode is activated for the entire port a. the interme- diate tri-state cycle is then inserted when writing ddran to make an output. for further information, see ?break-before-make switching? on page 46 . 10.4.2 puea ? port a pull-up enable control register 10.4.3 porta ? port a data register 10.4.4 ddra ? port a data direction register 10.4.5 pina ? port a input pins 10.4.6 pueb ? port b pull-up enable control register bit 7 6 5 4 3 2 1 0 0x08 ? ? ? ? ? ? bbmb bbma portcr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x03 puea7 puea6 puea5 puea4 puea3 puea2 puea1 puea0 puea read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x02 porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x01 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x00 pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x07 ? ? ? ? pueb3 pueb2 pueb1 pueb0 pueb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 59 8235b?avr?04/11 attiny20 10.4.7 portb ? port b data register 10.4.8 ddrb ? port b data direction register 10.4.9 pinb ? port b input pins bit 76543210 0x06 ? ? ? ? portb3 portb2 portb1 portb0 portb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x05 ? ? ? ? ddb3 ddb2 ddb1 ddb0 ddrb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x04 ? ? ? ? pinb3 pinb2 pinb1 pinb0 pinb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 n/a n/a n/a n/a 60 8235b?avr?04/11 attiny20 11. 8-bit timer/counter0 with pwm 11.1 features ? two independent output compare units ? double buffered outp ut compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 11.2 overview timer/counter0 is a general purpose 8-bit time r/counter module, with two independent output compare units, and with pwm support. it allows accurate program execution timing (event man- agement) and wave generation. a simplified block diagram of the 8-bit timer/counter is shown in figure 11-1 on page 60 . for the actual placement of i/o pins, refer to figure 1-1 on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca- tions are listed in the ?register description? on page 71 . figure 11-1. 8-bit timer/counter block diagram clock select timer/counter data b u s ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 61 8235b?avr?04/11 attiny20 11.2.1 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in figure 11-1 ) signals are all visible in the timer interrupt flag register (tif r). all interrupts are individually masked with the timer inter- rupt mask register (timsk). tifr and timsk are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) is compared with the timer/counter value at all times. the result of the compare can be used by the waveform gen- erator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b). see ?output compare unit? on page 62 for details. the compare match event will also set the compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 11.2.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a or compare unit b. howe ver, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. the definitions in table 11-1 are also used extensively throughout the document. 11.3 clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs0[2:0]) bits located in the timer/counter control register (tccr0b). for details on clock sources and pres- caler, see ?timer/counter prescaler? on page 105 . 11.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 11-2 on page 62 shows a block diagram of the counter and its surroundings. table 11-1. definitions constant description bottom the counter reaches bottom when it becomes 0x00 max the counter reaches its maximum when it becomes 0xff (decimal 255) top the counter reaches the top when it become s equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assi gnment depends on the mode of operation 62 8235b?avr?04/11 attiny20 figure 11-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs0[2:0]). when no clock source is selected (cs0[2:0] = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are clos e connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc0a. for more details about advanced counting sequences and waveform generation, see ?modes of opera- tion? on page 65 . the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the wgm0[1:0] bits. tov0 can be used for generating a cpu interrupt. 11.5 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output compare flag (ocf0a or ocf0 b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is exe- cuted. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the matc h signal to generate an output according to operating mode set by the wgm0[2:0] bits and compare output mode (com0x[1:0]) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation. see ?modes of operation? on page 65 . data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 63 8235b?avr?04/11 attiny20 figure 11-3 on page 63 shows a block diagram of the output compare unit. figure 11-3. output compare unit, block diagram the ocr0x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the dou- ble buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is dis- abled the cpu will access the ocr0x directly. 11.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force out put compare (0x) bit. forcing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x[1:0] bits settings define whether the oc0x pin is set, cleared or toggled). 11.5.2 compare match bloc king by tcnt0 write all cpu write operations to the tcnt0 register will block any compare ma tch that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initial- ized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 11.5.3 using the output compare unit since writing tcnt0 in any mo de of operation will block all compare matches for one timer clock cycle, there are risks involved when ch anging tcnt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 ocfn x (int.req.) 8-bit comparator ocrnx ocnx data b u s tcntn wgmn[2:0] waveform generator top focn comnx[1:0] bottom 64 8235b?avr?04/11 attiny20 equals the ocr0x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is down-counting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output com- pare (0x) strobe bits in normal mode. the oc0x registers keep their values even when changing between waveform generation modes. be aware that the com0x[1:0] bits are not double buffered together with the compare value. changing the com0x[1:0] bits will take effect immediately. 11.6 compare match output unit the compare output mode (com0x[1:0]) bits have two functions. the waveform generator uses the com0x[1:0] bits for defining the output compare (oc0x) state at the next compare match. also, the com0x[1:0] bits control the oc0x pin output source. figure 11-4 on page 64 shows a simplified schematic of the logic affected by the com0x[1:0] bit setting. the i/o regis- ters, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affe cted by the com0x[1:0] bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 11-4. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc0x) from the waveform generator if either of the com0x[1:0] bits are set. however, the oc0x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction port ddr dq dq ocn pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focn clk i/o 65 8235b?avr?04/11 attiny20 register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visi- ble on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the out- put is enabled. note that some com0x[1:0] bit settings are reserved for certain modes of operation, see ?register description? on page 71 11.6.1 compare output mode and waveform generation the waveform generator uses the com0x[1:0] bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x[1:0] = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 11-2 on page 71 . for fast pwm mode, refer to table 11-3 on page 72 , and for phase correct pwm refer to table 11-4 on page 72 . a change of the com0x[1:0] bits state will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the force output compare bits. see ?tccr0b ? timer/counter contro l register b? on page 74 . 11.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm[2:0]) and compare output mode (com0x[1:0]) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. t he com0x[1:0] bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x[1:0] bits control whether the output should be set, cleared, or toggled at a compare match (see ?modes of operation? on page 65 ). for detailed timing information refer to figure 11-8 on page 70 , figure 11-9 on page 70 , figure 11-10 on page 70 and figure 11-11 on page 71 in ?timer/counter timing diagrams? on page 69 . 11.7.1 normal mode the simplest mode of operation is the normal mode (wgm0[2:0] = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 11.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm0[2:0] = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence 66 8235b?avr?04/11 attiny20 also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 11-5 on page 66 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then coun- ter (tcnt0) is cleared. figure 11-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a[1:0] = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. when ocr0a is se t to zero (0x00) the wa veform gene rated will have a maximum frequency of f clk_i/o /2. the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 11.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm0[2:0] = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bot- tom. top is defined as 0xff when wgm0[2:0] = 3, and ocr0a when wgm0[2:0] = 7. in non- inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the out- put is set on compare match and cleared at bottom. due to the single-slope operation, the tcntn ocna (toggle) ocnx interrupt flag set 1 4 period 2 3 (comna[1:0] = 1) f ocnx f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = 67 8235b?avr?04/11 attiny20 operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 11-6 on page 67 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the singl e-slope operation. the diagram includes non- inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes repre- sent compare matches between ocr0x and tcnt0. figure 11-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x[1:0] bits to two will produce a non-inverted pwm and an inverted pwm out- put can be generated by setting the com0x[1:0] to three: setting the com0a[1:0] bits to one allowes the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 11-3 on page 72 ). the actual oc0x value will only be vis- ible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0x register represents special cases when generating a pwm waveform output in the fast pwm mode. if ocr0x is set equal to bottom, t he output will be a tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx[1:0] = 2) (comnx[1:0] = 3) ocrnx interrupt flag set 4 5 6 7 f ocnxpwm f clk_i/o ntop 1 + () ? ---------------------------------- - = 68 8235b?avr?04/11 attiny20 narrow spike for each top+1 timer clock cycle. setting the ocr0x equal to top will result in a constantly high or low output (depending on the polarity of the output set by the com0x[1:0] bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting oc0a to toggle its logical level on each compare match (com0a[1:0] = 1). the waveform generated will have a maximum frequency of f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the output com- pare unit is enabled in the fast pwm mode. 11.7.4 phase correct pwm mode the phase correct pwm mode (wgm0[2:0] = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm0[2:0] = 1, and ocr0a when wgm0[2:0] = 5. in non- inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while down- counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. figure 11-7. phase correct pwm mode, timing diagram in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 11-7 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the tovn interr u pt fl a g s et ocnx interr u pt fl a g s et 1 2 3 tcntn period ocnx ocxn (comnx[1:0] = 2) (comnx[1:0] = 3 ) ocrnx upd a te 69 8235b?avr?04/11 attiny20 small horizontal line marks on the tcnt0 slop es represent compare matches between ocr0x and tcnt0. the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x[1:0] bits to tw o will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x[1:0] to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare ma tches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 11-4 on page 72 ). the actual oc0x value will only be visible on the port pin if the data direction for th e port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setti ng (or clearing) the oc0x register at com- pare match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0x register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0x is set equal to bottom, the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 11-7 on page 68 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guaratee symmetry around bottom. there are two cases that give a transition without compare match. ? ocr0x changes its value from top, like in figure 11-7 on page 68 . when the ocr0x value is top the ocnx pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocnx value at top must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr0x, and for that reason misses the compare match and hence the ocnx change that would have happened on the way up. 11.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 11-8 on page 70 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase cor- rect pwm mode. f ocnxpcpwm f clk_i/o 2 n top ------------------------------- - = 70 8235b?avr?04/11 attiny20 figure 11-8. timer/counter timing diagram, no prescaling figure 11-9 on page 70 shows the same timing data, but with the prescaler enabled. figure 11-9. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 11-10 on page 70 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 11-10. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 11-11 on page 71 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 71 8235b?avr?04/11 attiny20 figure 11-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) 11.9 register description 11.9.1 tccr0a ? timer/counter control register a ? bits 7:6 ? com0a[1:0] : compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a[1:0] bits are set, the oc0a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction r egister (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the fu nction of the com0a[1:0] bits depends on the wgm0[2:0] bit setting. table 11-2 shows the com0a[1:0] bit functionality when the wgm0[2:0] bits are set to a normal or ctc mode (non-pwm). table 11-3 shows com0a[1:0] bit functionality when wgm0[2:0] bits are set to fast pwm mode. ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 0x19 com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 11-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match 72 8235b?avr?04/11 attiny20 note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 66 for more details. table 11-4 shows com0a[1:0] bit functionality when wgm0[2:0] bits are set to phase correct pwm mode. note: 1. when ocr0a equals top and com0a1 is set, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 68 for more details. ? bits 5:4 ? com0b[1:0] : compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of com0b[1:0] bits are set, the oc0b output overrides the normal port functionality of the i/o pin it is connected to. the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the functi on of com0b[1:0] bits depend on wgm0[2:0] bit setting. table 11-5 shows com0b[1:0] bit functionality when wgm0[2:0] bits are set to normal or ctc mode (non-pwm). table 11-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected 01 wgm02 = 0: normal port o peration, oc0a disconnected wgm02 = 1: toggle oc0a on compare match 10 clear oc0a on compare match set oc0a at bottom (non-inverting mode) 11 set oc0a on compare match clear oc0a at bottom (inverting mode) table 11-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port operation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. table 11-5. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match 73 8235b?avr?04/11 attiny20 table 11-6 shows com0b[1:0] bit functionality when wgm0[2:0] bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 66 for more details. table 11-7 shows the com0b[1:0] bit functionality when the wgm0[2:0] bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 68 for more details. ? bits 3:2 ? res: reserved bits these bits are reserved and will always read zero. ? bits 1:0 ? wgm0[1:0] : waveform generation mode combined with the wgm02 bit found in the tccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of wave- form generation to be used, see table 11-8 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 65 ). table 11-6. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match, set oc0b at bottom (non-inverting mode) 11 set oc0b on compare match, clear oc0b at bottom (inverting mode) table 11-7. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. 74 8235b?avr?04/11 attiny20 note: 1. max = 0xff bottom = 0x00 11.9.2 tccr0b ? timer/counter control register b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a[1:0] bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a[1:0] bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit always reads as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b[1:0] bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b[1:0] bits that determines the effect of the forced compare. table 11-8. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/counter mode of operation top update of ocrx at tov flag set on (1) 0 0 0 0 normal 0xff immediate max 1001 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4100reserved ? ? ? 5101 pwm, phase correct ocra top bottom 6110reserved ? ? ? 7111fast pwm ocrabottomtop bit 7 6 5 4 3 2 1 0 0x18 foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 75 8235b?avr?04/11 attiny20 a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit always reads as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the attiny20 and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?tccr0a ? timer/counter control register a? on page 71 . ? bits 2:0 ? cs0[2:0]: clock select the three clock select bits select the clock source to be used by the timer/counter. if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 11.9.3 tcnt0 ? timer/counter register the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 11.9.4 ocr0a ? output compare register a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. table 11-9. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x17 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x16 ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 76 8235b?avr?04/11 attiny20 11.9.5 ocr0b ? output compare register b the output compare register b contains an 8-bi t value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. 11.9.6 timsk ? timer/counter interrupt mask register ? bit 6 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enab led. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and th e i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter interrupt flag register ? tifr. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter interrupt flag register ? tifr. 11.9.7 tifr ? timer/counter interrupt flag register ? bit 6 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 2 ? ocf0b: output compare flag 0 b the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the cor- responding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to bit 76543210 0x15 ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543 2 10 0x26 icie1 ? ocie1b ocie1a toie1 ocie0b ocie0a toie0 timsk read/write r/w r r/w r/w r/w r/w r/w r/w initial value00000 0 00 bit 76543210 0x25 icf1 ? ocf1b ocf1a tov1 ocf0b ocf0a tov0 tifr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 77 8235b?avr?04/11 attiny20 the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: output compare flag 0 a the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the cor- responding interrupt handling vector. alternativel y, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm0[2:0] bit setting. see table 11-8 on page 74 and ?waveform generation mode bit description? on page 74 . 78 8235b?avr?04/11 attiny20 12. 16-bit timer/counter1 12.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered outp ut compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 12.2 overview the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. a simplified block diagram of the 16-bit timer/counter is shown in figure 12-1 on page 78 . for actual placement of i/o pins, refer to ?pinout of attiny20? on page 2 . cpu accessible i/o regis- ters, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in section ?register description? on page 99 . figure 12-1. 16-bit timer/counter block diagram clock s elect timer/co u nter data b u s ocrna ocrnb icrn = = tcntn w a veform gener a tion w a veform gener a tion ocna ocnb noi s e c a nceler icpn = fixed top v a l u e s edge detector control logic = 0 top bottom co u nt cle a r direction tovn (int.re q .) ocna (int.re q .) ocnb (int.re q .) icfn (int.re q .) tccrna tccrnb ( from an a log comp a r a tor o u p u t ) tn edge detector ( from pre s c a ler ) clk tn 79 8235b?avr?04/11 attiny20 most register and bit references in this sect ion are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. 12.2.1 registers the timer/counter (tcnt1), output compare registers (ocr1a/b), and input capture regis- ter (icr1) are all 16-bit registers. special procedures must be followed when accessing the 16- bit registers. these procedures are described in section ?accessing 16-bit registers? on page 95 . the timer/counter control registers (tccr1a/b) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr). all interrupts are individually masked with the timer interrupt mask register (timsk). tifr and timsk are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t1 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t1 ). the double buffered output compare registers (ocr1a/b) are compared with the timer/coun- ter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pin (oc1a/b). see ?out- put compare units? on page 83 . the compare match event will also set the compare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. the input capture register can capture the timer/ counter value at a given external (edge trig- gered) event on either the input capture pin (i cp1) or on the analog comparator pins (see ?analog comparator? on page 108 ). the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr1a register, the icr1 regist er, or by a set of fixed values. when using ocr1a as top value in a pwm mode, the ocr1a register can not be used for generating a pwm output. however, the top value will in this case be do uble buffered allowing the top value to be changed in run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as pwm output. 12.2.2 definitions the following definitions are used extensively throughout the section: table 12-1. definitions constant description bottom the counter reaches bottom when it becomes 0x00 max the counter reaches its maximum when it becomes 0xff (decimal 255) top the counter reaches top when it become s equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max), the value stored in the ocr 1 a register, or the value stored in the icr1 register. the assignment depends on the mode of operation 80 8235b?avr?04/11 attiny20 12.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs1[2:0]) bits located in the timer/counter control register b (tccr1b). for details on clock sources and prescaler, see ?timer/counter prescaler? on page 105 . 12.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 12-2 shows a block diagram of the counter and its surroundings. figure 12-2. counter unit block diagram description of internal signals used in figure 12-2 : count increment or decrement tcnt1 by 1. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t1 timer/counter1 clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) con- taining the upper eight bits of the counter, and counter low (tcnt1l) containing the lower eight bits. the tcnt1h register can only be indirect ly accessed by the cpu. when the cpu does an access to the tcnt1h i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register va lue when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will gi ve unpredictable results. the s pecial cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t1 ). the clk t1 can be generated from an external or internal clock source, selected by the clock select bits (cs1[2:0]). when no clock source is selected (cs1[2:0] = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 81 8235b?avr?04/11 attiny20 the counting sequence is determined by the setting of the waveform generation mode bits (wgm1[3:0]) located in the timer/counter control registers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc1x. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 86 . the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the wgm1[3:0] bits. tov1 can be used for generating a cpu interrupt. 12.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icp1 pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 12-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 12-3. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icp1), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a captur e is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf1) is set at the same system clock as the tcnt1 value is copi ed into icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capt ure interrupt. the icf1 flag is automatically icfn (int.re q .) an a log comp a r a tor write icrn (16- b it regi s ter) icrnh ( 8 - b it) noi s e c a nceler icpn edge detector temp ( 8 - b it) data b u s ( 8 - b it) icrnl ( 8 - b it) tcntn (16- b it co u nter) tcntnh ( 8 - b it) tcntnl ( 8 - b it) acic* icncn ice s 1 aco* 82 8235b?avr?04/11 attiny20 cleared when the interrupt is executed. alternativ ely the icf1 flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icr1) is done by first reading the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is copied into the high byte temporary regi ster (temp). when the cpu reads the icr1h i/o location it will access the temp register. the icr1 register can only be written when us ing a waveform generation mode that utilizes the icr1 register for defining the counter?s top value. in these cases the waveform genera- tion mode (wgm1[3:0]) bits must be set before the top value can be written to the icr1 register. when writing the icr1 re gister the high byte must be written to the icr1h i/o location before the low byte is written to icr1l. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 95 . 12.5.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp1). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp1) and the analog comparator output (aco) inputs are sampled using the same technique as for the t1 pin ( figure 13-1 on page 105 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases t he delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabl ed unless the timer/counter is set in a wave- form generation mode that uses icr1 to define top. an input capture can be trigger ed by software by controlling the port of the icp1 pin. 12.5.2 noise canceler the noise canceler uses a simple digital filter ing technique to improve noise immunity. consecu- tive samples are monitored in a pipeline four units deep. the signal going to the edge detecter is allowed to change only when all four samples are equal. the noise canceler is enabled by setting the input captur e noise canceler (icnc1) bit in timer/counter control register b (tccr1b). when enabled, the noise canceler introduces an additional delay of four system clock cycles to a change applied to the input and before icr1 is updated. the noise canceler uses the system clock directly and is therefore not affected by the prescaler. 12.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icr1 register before the nex t event occurs, the icr1 will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture interrupt, the icr1 register should be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high 83 8235b?avr?04/11 attiny20 priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 12.6 output compare units the 16-bit comparator continuously compares tcnt1 with the output compare register (ocr1x). if tcnt equals ocr1x the comparator signals a match. a match will set the output compare flag (ocf1x) at the next timer clock cycle. if enabled (ocie1x = 1), the output com- pare flag generates an output compare interrupt. the ocf1x flag is automatically cleared when the interrupt is executed. alternatively the ocf1x flag can be cleare d by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgm1[3:0]) bits and compare output mode (com1x[1:0]) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 86 ). a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 12-4. output compare unit, block diagram ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx[1:0] wgmn[ 3 :0] ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 84 8235b?avr?04/11 attiny20 figure 12-4 on page 83 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the ?x? indi- cates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. the ocr1x register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr1x com- pare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the out- put glitch-free. the ocr1x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr1x buffer register, and if double buffering is dis- abled the cpu will access the ocr1x directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocr1x registers must be done via the temp reg- ister since the compare of all 16 bits is done continuously. the high byte (ocr1xh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low by te (ocr1xl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr1x bu ffer or ocr1x compare register in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 95 . 12.6.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (1x) bit. forcing compare match will not set the ocf1x flag or reload/clear the timer, but the oc1x pin will be updated as if a real compare match had occurred (the com1[1:0] bits settings define whether the oc1x pin is set, cleared or toggled). 12.6.2 compare match bloc king by tcnt1 write all cpu writes to the tcnt1 register will block any compare match that o ccurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr1x to be initialized to the same value as tcnt1 without triggering an inte rrupt when the timer/counter clock is enabled. 12.6.3 using the output compare unit since writing tcnt1 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt1 when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare matc h will be missed, resulting in incorrect wave- form generation. do not write the tcnt1 equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counte r will continue to 0xffff. similarly, do not write the tcnt1 value equal to bottom when the counter is downcounting. the setup of the oc1x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc1x value is to use the force output com- 85 8235b?avr?04/11 attiny20 pare (1x) strobe bits in normal mode. the oc1x register keeps its value even when changing between waveform generation modes. be aware that the com1x[1:0] bits are not double buffered together with the compare value. changing the com1x[1:0] bits will take effect immediately. 12.7 compare match output unit the compare output mode (com1x[1:0]) bits have two functions. the waveform generator uses the com1x[1:0] bits for defining the output compare (oc1x) state at the next compare match. secondly the com1x[1:0] bits control the oc1x pin output source. figure 12-5 shows a simplified schematic of the logic affected by the com1x[1:0] bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x[1:0] bits are shown. when referring to the oc1x state, the reference is for the inter nal oc1x register, not the oc1x pin. if a system reset occur, the oc1x register is reset to ?0?. figure 12-5. compare match output unit, schematic (non-pwm mode) the general i/o port function is overridden by the output compare (oc1x) from the waveform generator if either of the com1x[1:0] bits are set. however, the oc1x pin direction (input or out- put) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc1x pin (ddr_oc1x) must be set as output before the oc1x value is visi- ble on the pin. the port override function is generally independent of the waveform generation mode, but there are some exceptions. see table 12-2 on page 99 , table 12-3 on page 99 and table 12-4 on page 100 for details. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 86 8235b?avr?04/11 attiny20 the design of the output compare pin logic allows initialization of the oc1x state before the out- put is enabled. note that some com1x[1:0] bit settings are reserved for certain modes of operation. see ?register description? on page 99 the com1x[1:0] bits have no effect on the input capture unit. 12.7.1 compare output mode and waveform generation the waveform generator uses the com1x[1:0] bits differently in normal, ctc, and pwm modes. for all modes, setting the com1x[1:0] = 0 tells the waveform generator that no action on the oc1x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 12-2 on page 99 . for fast pwm mode refer to table 12-3 on page 99 , and for phase correct and phase and frequency correct pwm refer to table 12-4 on page 100 . a change of the co m1x[1:0] bits state will have effect at the first compare ma tch after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc1x strobe bits. 12.8 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm1[3:0]) and compare out- put mode (com1x[1:0]) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com1x[1:0] bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non- pwm modes the com1x[1:0] bits control whether the output should be set, cleared or toggle at a compare match ( ?compare match output unit? on page 85 ) for detailed timing information refer to ?timer/counter timing diagrams? on page 93 . 12.8.1 normal mode the simplest mode of operation is the normal mode (wgm1[3:0] = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/c ounter overflow flag (tov1) will be set in the same timer clock cycle as the tcnt1 beco mes zero. the tov1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generat e interrupts at some given time. using the output compare to gene rate waveforms in norm al mode is not recommended, since this will occupy too much of the cpu time. 12.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm1[3:0] = 4 or 12), the ocr1a or icr1 register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when 87 8235b?avr?04/11 attiny20 the counter value (tcnt1) matches either the ocr1a (wgm1[3:0] = 4) or the icr1 (wgm1[3:0] = 12). the ocr1a or icr1 define the top value for the counter, hence also its res- olution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 12-6 on page 87 . the counter value (tcnt1) increases until a compare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. figure 12-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocf1a or icf1 flag according to the register used to define the top value. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom w hen the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr1a or icr1 is lower than the current value of tcnt1, the counter will miss the compare matc h. the counter will th en have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocr1a for defining top (wgm1[ 3:0] = 15) since the ocr1a then will be doub le buffered. for generating a waveform output in ctc mode, the oc1a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com1a[1:0] = 1). the oc1a value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_oc1a = 1). the waveform g enerated will have a maximum fre- quency of f clk_i/o /2 when ocr1a is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov1 flag is set in the same timer clock cycle that the counter counts from max to 0x0000. tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna[1:0] = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? --------------------------------------------------- = 88 8235b?avr?04/11 attiny20 12.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm1[3:0] = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x, and set at bottom. in inverting compare output mode output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase cor- rect and phase and frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regula tion, rectification, and dac applications. high frequency allows physically sm all sized external com ponents (coils, capaci- tors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the max- imum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm1[3:0] = 5, 6, or 7), the value in icr1 (wgm1[3:0] = 14), or the value in ocr1a (wgm1[3:0] = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 12-7 on page 88 . the figure shows fast pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. figure 12-7. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches top. in addition the oc1a or icf1 flag is set at the same timer clock cycle as tov1 is set when either ocr1a or r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx[1:0] = 2) (comnx[1:0] = 3) 89 8235b?avr?04/11 attiny20 icr1 is used for defining the top value. if one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values the unused bits are masked to zero when any of the ocr1x registers are written. the procedure for updating icr1 differs from updating ocr1a when used for defining the top value. the icr1 register is not double buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value written is lower than the current va lue of tcnt1. the result will then be that the counter will miss the compare matc h at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr1a register however, is double buffered. this feature allows the ocr1a i/o location to be written anytime. when the ocr1a i/o location is written the value written will be put into the ocr1a buffer register. th e ocr1a compare register will th en be updated with the value in the buffer register at the next timer clo ck cycle the tcnt1 matches top. the update is done at the same timer clock cycle as the tcnt1 is cleared and the tov1 flag is set. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. however, if the base pwm frequency is actively change d (by changing the top value), using the ocr1a as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x[1:0] bits to two will produce a non-inverted pwm and an inverted pwm out- put can be generated by setting the com1x[1:0] to three (see table 12-3 on page 99 ). the actual oc1x value will only be visible on the port pi n if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x regis- ter at the compare match between ocr1x and tcnt1, and clearing (or setting) the oc1x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1x is set equal to bottom (0x0000) the out- put will be a narrow spike for eac h top+1 timer clock cycle. se tting the ocr1x equal to top will result in a const ant high or low output (depending on the polarity of the output set by the com1x[1:0] bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting oc1a to toggle its logical level on each compare match (com1a[1:0] = 1). the waveform generated will have a ma ximum frequency of f clk_i/o /2 when ocr1a is set to zero (0x0000). this feature is similar to the oc1a toggle in ctc mode, except the double buffer feature of the out- put compare unit is enabled in the fast pwm mode. f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = 90 8235b?avr?04/11 attiny20 12.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgm1[3:0] = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feat ure of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolu- tion in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm1[3:0] = 1, 2, or 3), the value in icr1 (wgm1[3:0] = 10), or the value in ocr1a (wgm1[3:0] = 11). the counter has then reached the top and changes the count direct ion. the tcnt1 value will be equa l to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 12-8 . the figure shows phase correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrati ng the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x inter- rupt flag will be set when a compare match occurs. figure 12-8. phase correct pwm mode, timing diagram r pcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx[1:0] = 2) (comnx[1:0] = 3) 91 8235b?avr?04/11 attiny20 the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag is set accord- ingly at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values, the unus ed bits are masked to zero when any of the ocr1x registers are written. as the third period shown in figure 12-8 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocr1x reg- ister. since the ocr1x update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by th e new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x[1:0] bits to tw o will produce a non-invert ed pwm and an inverted pwm output can be generated by setting the com1x[1:0] to three (see table 12-4 on page 100 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm wavefo rm is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter incre- ments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pw m frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. 12.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgm1[3:0] = 8 or 9) provides a high resolution phase and frequency correct pwm wave- form generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation fre- f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = 92 8235b?avr?04/11 attiny20 quency compared to the single-slope operation. howe ver, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocr1x register is up dated by the ocr1x buffer register, (see figure 12- 8 on page 90 and figure 12-9 on page 92 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1 a set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icr1 (wgm1[3:0] = 8), or the value in ocr1a (wgm1[3:0] = 9). the counter has then reac hed the top and ch anges the count di rection. the tcnt1 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 12-9 . the figure shows phase and frequency correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing dia- gram shown as a histogram for illustrating the dual-slope operati on. the diagram includes non- inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes repre- sent compare matches between oc r1x and tcnt1. the oc1x inte rrupt flag will be set when a compare match occurs. figure 12-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at bottom). when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag set when tcnt1 has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. r pfcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx[1:0] = 2) (comnx[1:0] = 3) 93 8235b?avr?04/11 attiny20 when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will neve r occur between the tcnt1 and the ocr1x. as figure 12-9 shows the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. since the ocr1x registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. however, if the base pwm frequency is actively changed by changing the top value, using the ocr1a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm wave- forms on the oc1x pins. setting the com1x[1:0] bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com1x[1:0] to three (see table 12-4 on page 100 ). the actual oc1x value will only be visibl e on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the coun- ter increments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pwm frequency for the output when using phase and frequency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non- inverted pwm mode. for inverted pwm the output will have the opposite logic values. 12.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocr1x register is updated with the ocr1x buffer value (only for modes utilizing double buffering). figure 12-10 shows a timing diagram for the setting of ocf1x. f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 94 8235b?avr?04/11 attiny20 figure 12-10. timer/counter timing diagram, setting of ocf1x, no prescaling figure 12-11 shows the same timing data, but with the prescaler enabled. figure 12-11. timer/counter timing diagram, setting of ocf1x, with prescaler (f clk_i/o /8) figure 12-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocr1x register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tov1 flag at bottom. tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 95 8235b?avr?04/11 attiny20 figure 12-12. timer/counter timing diagram, no prescaling figure 12-13 shows the same timing data, but with the prescaler enabled. figure 12-13. timer/counter timing dia gram, with prescaler (f clk_i/o /8) 12.10 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high by te of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low byte is read. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 96 8235b?avr?04/11 attiny20 not all 16-bit accesses uses the temporary register for the high byte. reading the ocr1a/b 16- bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr1a/b and icr1 registers. note that when using ?c?, the compiler handles the 16-bit access. note: see ?code examples? on page 6 . the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. assembly code example ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 1 h,r17 out tcnt 1 l,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ... c code example unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... 97 8235b?avr?04/11 attiny20 note: see ?code examples? on page 6 . the assembly code example returns the tcnt1 value in the r17:r16 register pair. the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b or icr1 register s can be done by using the same principle. assembly code example tim16_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ; restore global interrupt flag out sreg,r18 ret c code example unsigned int tim16_readtcnt 1 ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt 1 into i */ i = tcnt 1 ; /* restore global interrupt flag */ sreg = sreg; return i; } 98 8235b?avr?04/11 attiny20 note: see ?code examples? on page 6 . the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt1. 12.10.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example tim16_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tcnt 1 h,r17 out tcnt 1 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example void tim16_writetcnt 1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt 1 to i */ tcnt 1 = i; /* restore global interrupt flag */ sreg = sreg; } 99 8235b?avr?04/11 attiny20 12.11 register description 12.11.1 tccr1a ? timer/counter1 control register a ? bits 7:6 ? com1a[1:0] : compare output mode for channel a ? bits 5:4 ? com1b[1:0] : compare output mode for channel b the com1a[1:0] and com1b[1:0] control the output compare pins (oc1a and oc1b respec- tively) behavior. if one or both of the com1a[1:0] bits are written to one, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the com1b[1:0] bit are written to one, the oc1b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond- ing to the oc1a or oc1b pin must be set in order to enable the output driver. when the oc1a or oc1b is connected to the pin, the function of the com1x[1:0] bits is depen- dent of the wgm1[3:0] bits setting. table 12-2 shows com1x[1:0] bit functionality when wgm1[3:0] bits are set to a normal or a ctc mode (non-pwm). table 12-3 shows com1x[1:0] bit functionality when wgm1[3:0] bits are set to fast pwm mode. note: a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set. in this case the compare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 88 for more details. bit 7 6 5 4 3 2 1 0 0x24 com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 12-2. compare output mode, non-pwm com1a1 com1b1 com1a0 com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected 0 1 toggle oc1a/oc1b on compare match 10 clear oc1a/oc1b on compare match (set output to low level) 11 set oc1a/oc1b on compare match (set output to high level). table 12-3. compare output mode, fast pwm com1a1 com1b1 com1a0 com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected 01 wgm13=0: normal port operation, oc1a/oc1b disconnected wgm13=1: toggle oc1a on compare match, oc1b reserved 10 clear oc1a/oc1b on compare match, set oc1a/oc1b at bottom (non-inverting mode) 11 set oc1a/oc1b on compare match, clear oc1a/oc1b at bottom (inverting mode) 100 8235b?avr?04/11 attiny20 table 12-4 shows com1x[1:0] bit functionality when wgm1[3:0] bits are set to phase correct or phase and frequency correct pwm mode. note: a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set. ?phase correct pwm mode? on page 90 for more details. ? bits 1:0 ? wgm1[1:0]: waveform generation mode combined with the wgm1[3:2] bits found in the tccr1b register, these bits control the count- ing sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 12-5 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( ?modes of operation? on page 86 ). table 12-4. compare output mode, phase correct and phase & frequency correct pwm com1a1 com1b1 com1a0 com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected 01 wgm13=0: normal port operation, oc1a/oc1b disconnected wgm13=1: toggle oc1a on compare match, oc1b reserved 10 clear oc1a/oc1b on compare match when up-counting set oc1a/oc1b on compare match when downcounting 11 set oc1a/oc1b on compare match when up-counting clear oc1a/oc1b on compare match when downcounting table 12-5. waveform generation modes mode wgm1 [3:0] mode of operation top update of ocr1 x at tov1 flag set on 0 0000 normal 0xffff immediate max 1 0001 pwm, phase correct, 8-bit 0x00ff top bottom 2 0010 pwm, phase correct, 9-bit 0x01ff top bottom 3 0011 pwm, phase correct, 10-bit 0x03ff top bottom 40100ctc ( clear timer on compare ) ocr1a immediate max 5 0101 fast pwm, 8-bit 0x00ff top top 6 0110 fast pwm, 9-bit 0x01ff top top 7 0111 fast pwm, 10-bit 0x03ff top top 8 1000 pwm, phase & freq. correct icr1 bottom bottom 9 1001 pwm, phase & freq. correct ocr1a bottom bottom 10 1010 pwm, phase correct icr1 top bottom 11 1011 pwm, phase correct ocr1a top bottom 12 1100 ctc ( clear timer on compare ) icr1 immediate max 13 1101 (reserved) ? ? ? 14 1110 fast pwm icr1 top top 15 1111 fast pwm ocr1a top top 101 8235b?avr?04/11 attiny20 12.11.2 tccr1b ? timer/counter1 control register b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input capt ure noise canceler. when the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) that is used to trigger a capture event. when the ices1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices1 bit is written to one, a risi ng (positive) edge w ill trigger the capture. when a capture is triggered according to the ices1 setting, the counter value is copied into the input capture register (icr1). the event will also set the input capture flag (icf1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icr1 is used as top value (see descri ption of the wgm1[3:0] bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and consequently the input cap- ture function is disabled. ? bit 5 ? res: reserved bit this bit is reserved for future use. for ensuring compatibility with future de vices, this bit must be written to zero when tccr1b is written. ? bits 4:3 ? wgm1[3:2] : waveform generation mode see tccr1a register description. ? bits 2:0 ? cs1[2:0]: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 12-10 on page 94 and figure 12-11 on page 94 . bit 7654 3210 0x23 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 12-6. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin. clock on falling edge. 1 1 1 external clock source on t1 pin. clock on rising edge. 102 8235b?avr?04/11 attiny20 if external pin modes are used for the timer/counter1, transitions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 12.11.3 tccr1c ? timer/counter1 control register c ? bit 7 ? foc1a: force output compare for channel a ? bit 6 ? foc1b: force output compare for channel b the foc1a/foc1b bits are only active when the wgm1[3:0] bits specifies a non-pwm mode. however, for ensuring compatibility with future devices, these bits must be set to zero when tccr1a is written when operating in a pwm mode. when writing a logical one to the foc1a/foc1b bit, an immediate compare match is forced on the waveform generation unit. the oc1a/oc1b output is changed according to its com1x[1:0] bits setting. note that the foc1a/foc1b bits are implemented as strobes. therefore it is the value present in the com1x[1:0] bits that determine the effect of the forced compare. a foc1a/foc1b strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as zero. ? bits 5:0 ? res: reserved bit these bits are reserved for future use. to ensure compatibility with future devices, these bits must be set to zero when the register is written. 12.11.4 tcnt1h and tcnt1l ? timer/counter1 the two timer/counter i/o locations (tcnt1 h and tcnt1l, combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfo rmed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 95 . modifying the counter (tcnt1) while the counte r is running introduces a risk of missing a com- pare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (removes) the compare match on the following timer clock for all compare units. bit 7654 3210 0x22 foc1a foc1b ? ? ? ? ? ? tccr1c read/write w w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 0x21 tcnt1[15:8] tcnt1h 0x20 tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 103 8235b?avr?04/11 attiny20 12.11.5 ocr1ah and ocr1al ? ou tput compare register 1 a 12.11.6 ocr1bh and ocr1bl ? ou tput compare register 1 b the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1x pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cp u writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16- bit registers. see ?accessing 16-bit registers? on page 95 . 12.11.7 icr1h and icr1l ? input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. ?accessing 16-bit registers? on page 95 . 12.11.8 timsk ? timer/counter interrupt mask register ? bit 7 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern input capture interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 66.) is executed when the icf1 flag, located in tifr, is set. ? bit 5 ? ocie1b: timer/counter1, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding bit 76543210 0x1f ocr1a[15:8] ocr1ah 0x1e ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x1d ocr1b[15:8] ocr1bh 0x1c ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x1b icr1[15:8] icr1h 0x1a icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 0x26 icie1 ? ocie1b ocie1a toie1 ocie0b ocie0a toie0 timsk read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 104 8235b?avr?04/11 attiny20 interrupt vector (see ?interrupts? on page 38 ) is executed when the ocf1b flag, located in tifr, is set. ? bit 4 ? ocie1a: timer/counter1, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 38 ) is executed when the ocf1a flag, located in tifr, is set. ? bit 3 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 38 ) is executed when the tov1 flag, located in tifr, is set. 12.11.9 tifr ? timer/counter interrupt flag register ? bit 7 ? icf1: timer/count er1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgm1[3:0] to be used as the top value, the icf1 flag is set when the coun- ter reaches the top value. icf1 is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 5 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (1 b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compare match b interrupt vector is exe- cuted. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 4 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (1 a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compare match a interrupt vector is exe- cuted. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 3 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the wgm1[3:0] bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. see table 12-5 on page 100 for the tov1 flag behavior when using another wgm1[3:0] bit setting. tov1 is automatically cleared when the timer/c ounter1 overflow interrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 765432 1 0 0x25 icf1 ?ocf1bocf1atov1 ocf0b ocf0a tov0 tifr read/write r/w r r/w r/w r/w r/w r/w r/w initial value000000 0 0 105 8235b?avr?04/11 attiny20 13. timer/counter prescaler timer/counter0 and timer/counter1 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counters. tn is used as a general name, n = 0, 1. the timer/counter can be clocked directly by the system clock (by setting the csn[2:0] = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 13.1 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/countercounter, and it is shared by the timer/counter tn. since the prescaler is not affected by the timer/counter?s cl ock select, the state of the pres caler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (csn[2:0] = 2, 3, 4, or 5). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 sys- tem clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execution. 13.2 external clock source an external clock source applied to the tn pin can be used as timer/counter clock (clk tn ). the tn pin is sampled once every system clock cycle by the pin synchronization logic. the synchro- nized (sampled) signal is then passed through the edge detector. figure 13-1 shows a functional equivalent block diagram of the tn synchroniza tion and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t 0 pulse for each positive (csn[2:0] = 7) or negative (csn[2:0] = 6) edge it detects. figure 13-1. t0 pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn pin to the counter is updated. tn_ s ync (to clock s elect logic) edge detector s ynchroniz a tion dq dq le dq tn clk i/o 106 8235b?avr?04/11 attiny20 enabling and disabling of the clock input must be done when tn has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 13-2. prescaler for timer/counter0 note: 1. the synchronization logic on the input pins ( t0) is shown in figure 13-1 on page 105 . p s r cle a r clk t0 t0 clk i/o s ynchroniz a tion 107 8235b?avr?04/11 attiny20 13.3 register description 13.3.1 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psr bit is kept, hence keeping the prescaler reset signal asserted. this ensures that the timer/counter is halted and can be configured without the risk of advanc- ing during configuration. when the tsm bit is written to zero, the psr bit is cleared by hardware, and the timer/counter start counting. ? bit 0 ? psr: prescaler reset when this bit is one, the timer/counter presca ler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. bit 7 6 5 4 3 2 1 0 0x27 tsm ? ? ? ? ? ? psr gtccr read/write r/w r r r r r r r/w initial value 0 0 0 0 0 0 0 0 108 8235b?avr?04/11 attiny20 14. analog comparator the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator can trigger a separate inter- rupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of t he comparator and its surrounding logic is shown in figure 14-1 . figure 14-1. analog comparator block diagram notes: 1. see table 14-1 on page 109 . see figure 1-1 on page 2 and table 10-9 on page 57 for analog comparator pin placement. the adc power reduction bit, pradc, must be disabled in order to use the adc input multi- plexer. this is done by clearing the pradc bi t in the power reduction register, prr. see ?prr ? power reduction register? on page 29 for more details. acbg aco bandgap reference adc multiplexer output to t/c1 capture trigger mux acic acme (1) hsel hlev 109 8235b?avr?04/11 attiny20 14.1 analog comparator multiplexed input when the analog to digital converter (adc) is configurated as single ended input channel, it is possible to select any of the adc[7:0] pins to replace the negative input to the analog compara- tor. the adc multiplexer is used to select this input. if the analog comparator multiplexer enable bit (acme in adcsrb) is set, mux bits in admux select the input pin to replace the negative input to the analog comparator. 14.2 register description 14.2.1 acsra ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable when this bit is written logic one , the power to the analog comparator is switched off. this bit can be set at any time to tu rn off the analog com parator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed, internal bandgap reference voltage replaces the positive input to the analog comparator. when this bit is cleared, ain0 is applied to the positive input of the analog comparator. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. table 14-1. analog comparator multiplexed input acme mux[3:0] analog comp arator negative input 0 xxxx ain1 1 0000 adc0 1 0001 adc1 1 0010 adc2 1 0011 adc3 1 0100 adc4 1 0101 adc5 1 0110 adc6 1 0111 adc7 bit 76543210 0x14 acd acbg aco aci acie acic acis1 acis0 acsra read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 110 8235b?avr?04/11 attiny20 ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bi t in the status register is set, the analog com- parator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator output is then directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select fea- tures of the timer/counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture inter-rupt, the icie1 bit in the timer interrupt mask register (timsk) must be set. ? bits 1:0 ? acis[1:0]: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 14-2 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. 14.2.2 acsrb ? analog comparator control and status register b ? bit 7 ? hsel: hysteresis select when this bit is written logic one, the hysteresis of the analog comparator is enabled. the level of hysteresis is selected by the hlev bit. table 14-2. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 7 6543210 0x13 hsel hlev aclp ? acce acme acirs1 acirs0 acsrb read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0000000 111 8235b?avr?04/11 attiny20 ? bit 6 ? hlev: hysteresis level when enabled via the hsel bit, the level of hysteresis can be set using the hlev bit, as shown in table 14-3 . ? bit 5 ? aclp this bit is reserved for qtouch, always write as zero. ? bit 4 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 3 ? acce this bit is reserved for qtouch, always write as zero. ? bit 2 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 109 . ? bit 1 ? acirs1 this bit is reserved for qtouch, always write as zero. ? bit 0 ? acirs0 this bit is reserved for qtouch, always write as zero. 14.2.3 didr0 ? digital in put disable register 0 ? bits 2:1 ? adc2d, adc1d: adc 2/1 digital input buffer disable when this bit is written logic one, the digital input buffer on the ain1/0 pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when used as an analog input but not required as a digital input the power consumption in the digital input buffer can be reduced by writing this bit to logic one. table 14-3. selecting level of analog comparator hysteresis hsel hlev hysteresis of analog comparator 0 x not enabled 1 020 mv 150 mv bit 76543210 0x0d adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 112 8235b?avr?04/11 attiny20 15. analog to digital converter 15.1 features ? 10-bit resolution ? 1 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13s conversion time ? 15 ksps at maximum resolution ? eight multiplexed single ended input channels ? temperature sensor input channel ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? 1.1v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto tr iggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode no ise canceler 15.2 overview attiny20 features a 10-bit, successive approximation analog-to-digital converter (adc). the adc is wired to a nine-channel analog multiplexe r, which allows the adc to measure the volt- age at eight single-ended input pins, or from one internal, single-ended voltage channel coming from the internal temperature sensor. voltage inputs are referred to 0v (gnd). the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 15-1 on page 113 . internal reference voltage of nominally 1.1v is provided on-chip. alternatively, v cc can be used as reference voltage for single ended channels. 113 8235b?avr?04/11 attiny20 figure 15-1. analog to digital converter block schematic 15.3 operation in order to be able to use the adc the power reduction bit, pradc, in the power reduction register must be disabled. this is done by clearing the pradc bit. see ?prr ? power reduc- tion register? on page 29 for more details. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. admux a d m u x decoder d e c o d e r 8-bit data bus mux[3:0] adcsra a d c s r a adch+adcl a d c h + a d c l adps0 aden adps1 adps2 adate adif adsc trigger t r i g g e r select s e l e c t adts[2:0] start prescaler p r e s c a l e r adc9:0 conversion logic c o n v e r s i o n l o g i c 10-bit dac 1 0 - b i t d a c adcsrb a d c s r b - + adc3 a d c 3 adc2 a d c 2 adc1 a d c 1 adc0 a d c 0 v cc c c input i n p u t mux m u x channel adie adc irq a d c i r q sample & hold s a m p l e & h o l d comparator c o m p a r a t o r internal i n t e r n a l reference r e f e r e n c e temperature t e m p e r a t u r e sensor s e n s o r agnd adc mux output a d c m u x o u t p u t refs interrupt flags adlar adc7 a d c 7 adc6 a d c 6 adc5 a d c 5 adc4 a d c 4 114 8235b?avr?04/11 attiny20 the adc converts an analog input voltage to a 10-bit digital value using successive approxima- tion. the minimum value represents gnd and the maximum value represents the reference voltage. the adc voltage reference is selected by writing the refs bit in the admux register. alternatives are the v cc supply pin and the internal 1.1v voltage reference. the analog input channel is selected by writing to the mux bits in admux. any of the adc input pins can be selected as single ended inputs to the adc. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in adcsrb. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch, only. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data regis- ters is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and th e result from the conversion is lost. when adch is read, adc access to the adch an d adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between r eading of adch and ad cl, the in terrupt will trigger even if the result is lost. 15.4 starting a conversion make sure the adc is powered by clearing the adc power reduction bit, pradc, in the power reduction register, prr (see ?prr ? power reduction register? on page 29 ). a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be star ted. if another positive edge occurs on the trigger si gnal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 115 8235b?avr?04/11 attiny20 figure 15-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 15.5 prescaling and conversion timing by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. it is not recommended to use a higher input clock frequency than 1 mhz. figure 15-3. adc prescaler the adc module contains a prescaler, as illustrated in figure 15-3 on page 115 , which gener- ates an acceptable adc clock frequency fr om any cpu frequency above 100 khz. the adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 116 8235b?avr?04/11 attiny20 prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by se tting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles, as summarised in table 15-1 on page 118 . the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry, as shown in figure 15-4 below. figure 15-4. adc timing diagram, first conver sion (single conversion mode) the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of a first conversion. see figure 15-5 . when a conversion is complete, the result is written to the adc data registers, and adif is set. in sin- gle conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the first rising adc clock edge. figure 15-5. adc timing diagram, single conversion when auto triggering is used, the prescaler is reset when the trigger event occurs, as shown in figure 15-6 below. this assures a fixed delay from the trigger event to the start of conversion. in sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 117 8235b?avr?04/11 attiny20 this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. figure 15-6. adc timing diagram, auto triggered conversion in free running mode, a new conversion will be started immediately after the conversion com- pletes, while adsc remains high. see figure 15-7 . figure 15-7. adc timing diagram, free running conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 12 13 14 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 118 8235b?avr?04/11 attiny20 for a summary of conversion times, see table 15-1 . 15.6 changing channel or reference selection the mux and refs bits in the admux register are single buffered through a temporary regis- ter to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion star ts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: ? when adate or aden is cleared. ? during conversion, minimum one adc clock cycle after the trigger event. ? after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. 15.6.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. ? in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the table 15-1. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 normal conversions 1.5 13 auto triggered conversions 2 13.5 free running conversion 2.5 14 119 8235b?avr?04/11 attiny20 channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selection. su bsequent conversions will reflect the new channel selection. 15.6.2 adc voltage reference the adc reference voltage (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either v cc , or internal 1.1v reference. the internal 1.1v reference is generated from the internal band- gap reference (v bg ) through an internal amplifier. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 15.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode. this reduces noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: ? make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. ? enter adc noise reduction mode (or idle mode ). the adc will start a conversion once the cpu has been halted. ? if no other interrupts occur be fore the adc conversion comple tes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, that interrupt will be executed, and an adc conversion complete interrup t request will be gene rated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not automatically be turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. 15.8 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 15-8 . an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals with an output impedance of approximately 10k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source nee ds to charge the s/h capacitor, which can vary widely. the user is recommended to only use low impedance sources with slowly varying signals, since this mi nimizes the required charge transfer to the s/h capacitor. 120 8235b?avr?04/11 attiny20 in order to avoid distortion from unpredictable si gnal convolution, signal components higher than the nyquist frequency (f adc /2) should not be present. the user is advised to remove high fre- quency components with a low-pa ss filter before applying the signals as inputs to the adc. figure 15-8. analog input circuitry note: the capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. the value given is worst case. 15.9 noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. when conversion accuracy is critical, the noise level can be reduced by applying the following techniques: ? keep analog signal paths as short as possible. ? make sure analog tracks run over the analog ground plane. ? keep analog tracks well away from high-speed switching digital tracks. ? if any port pin is used as a digital output, it mustn?t switch while a conversion is in progress. ? place bypass capacitors as close to v cc and gnd pins as possible. where high adc accuracy is required it is recommended to use adc noise reduction mode, as described in section 15.7 on page 119 . this is especially the case when system clock frequency is above 1 mhz, or when the adc is used for reading the internal temperature sensor, as described in section 15.12 on page 123 . a good system design with properly placed, external bypass capacitors does reduce the need for using adc noise reduction mode 15.10 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior, as follows: adcn i ih 1..100 k ohm c s /h = 14 pf v cc /2 i il 121 8235b?avr?04/11 attiny20 ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 15-9. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 15-10. gain error output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 122 8235b?avr?04/11 attiny20 ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 15-11. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 15-12. differential non-linearity (dnl) output code v ref input voltage ideal adc actual adc inl output code 0xff 0x00 0 v ref input voltage dnl 1 lsb 123 8235b?avr?04/11 attiny20 ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 15.11 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc data registers (adcl, adch). the result is, as follows: where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 15-3 on page 124 and table 15-4 on page 124 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. the result is presented in one- sided form, from 0x3ff to 0x000. 15.12 temperature measurement the temperature measurement is based on an on-ch ip temperature sensor that is coupled to a single ended adc channel. the temperature sensor is measured via channel adc8 and is enabled by writing mux bits in admux register to ?1010?. the internal 1.1v reference must also be selected for the adc reference source in the temperature sensor measurement. when the temperature sensor is enabled, the adc converter can be used in single conversion mode to measure the voltage over the temperature sensor. the measured voltage has a linear relationship to the temperature as described in table 15-2 the sensitivity is approximately 1 lsb / c and the accuracy depends on the method of user cal- ibration. typically, the measurement accuracy after a single temperature calibration is 10 c, assuming calibration at room temperature. better accuracies are achieved by using two temperature points for calibration. the values described in table 15-2 are typical values. however, due to process variation the temperature sensor output voltage varies from one chip to another. to be capable of achieving more accurate results the temperature measurement can be calibrated in the application soft- ware. the sofware calibration can be done using the formula: t = k * [(adch << 8) | adcl] + t os where adch and adcl are the adc data registers, k is the fixed slope coefficient and t os is the temperature sensor offset. typically, k is very close to 1.0 and in single-point calibration the coefficient may be omitted. where higher accura cy is required the slope coefficient should be evaluated based on measurements at two temperatures. adc v in 1024 ? v ref -------------------------- = table 15-2. temperature vs. sensor output voltage (typical case) temperature -40 c+25 c+85 c adc 230 lsb 300 lsb 370 lsb 124 8235b?avr?04/11 attiny20 15.13 register description 15.13.1 admux ? adc multiplexer selection register ? bit 7 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 6 ? refs: reference selection bit this bits selects the voltage reference for the adc, as shown in table 15-3 . if this bit is changed during a co nversion, the change will not go in effect until this conversion is complete (adif in adcsr is set). also note, that when these bits are changed, the next conversion will take 25 adc clock cycles. ? bit 5 ? refen this bit is reserved for qtouch, always write as zero. ? bit 4 ? adc0en this bit is reserved for qtouch, always write as zero. ? bits 3:0 ? mux[3:0] : analog channel and gain selection bits the value of these bits selects which analog input is connected to t he adc, as shown in table 15-4 . selecting channel adc8 enables temperature measurement. bit 765 4 3210 0x10 ? refs refen adc0en mux3 mux2 mux1 mux0 admux read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-3. voltage reference selections for adc refs voltage reference selection 0v cc used as analog reference 1 internal 1.1v voltage reference table 15-4. single-ended input channel selections. single ended input mux[3:0] adc0 (pa0) 0000 adc1 (pa1) 0001 adc2 (pa2) 0010 adc3 (pa3) 0011 adc4 (pa4) 0100 adc5 (pa5) 0101 adc6 (pa6) 0110 adc7 (pa7) 0111 0v (agnd) 1000 125 8235b?avr?04/11 attiny20 notes: 1. after switching to internal voltage refere nce the adc requires a settling time of 1ms before measurements are stable. conversions starting before this may not be reliable. the adc must be enabled during the settling time. 2. see ?temperature measurement? on page 123 . if these bits are changed during a conversion, the change will not go into effect until this conversion is complete (adif in adcsra is set). 15.13.2 adcl and adch ? adc data register 15.13.2.1 adlar = 0 15.13.2.2 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated unt il adch is read. consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in adcsrb, and t he mux bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. ? adc[9:0]: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 123 . internal 1.1v voltage reference (1) 1001 adc8 (temperature sensor) (2) 1010 reserved 1011 ? 1111 table 15-4. single-ended input channel selections. (continued) single ended input mux[3:0] bit 151413121110 9 8 0x0f ? ? ? ? ? ? adc9 adc8 adch 0x0e adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 151413121110 9 8 0x0f adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch 0x0e adc1 adc0 ? ? ? ? ? ? adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 126 8235b?avr?04/11 attiny20 15.13.3 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writi ng it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the norma l 13. this first conversi on performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. when the co nversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to on e, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if th e adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corres ponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete inter- rupt is activated. bit 76543210 0x12 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 127 8235b?avr?04/11 attiny20 ? bits 2:0 ? adps[2:0]: adc prescaler select bits these bits determine the division factor betwee n the system clock frequency and the input clock to the adc. 15.13.4 adcsrb ? adc control and status register b ? bit 7 ? vden this bit is reserved for qtouch, always write as zero. ? bit 6 ? vdpd this bit is reserved for qtouch, always write as zero. ? bits 5:4 ? res: reserved bits these are reserved bits. for comp atibility with future devices a lways write these bits to zero. ? bit 3 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affect t he adc data register immediately, regardless of any ongoing conver- sions. for a comple the description of this bit, see ?adcl and adch ? adc data register? on page 125 . ? bits 2:0 ? adts[2:0] : adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts[2:0] settings will have no effect. a conver- sion will be triggered by the rising edge of the selected in terrupt flag. note th at switching from a trigger source that is cleared to a trigger sour ce that is set, will generate a positive edge on the table 15-5. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 76543210 0x11 vden vdpd ? ? adlar adts2 adts1 adts0 adcsrb read/write r/w r/w r r r/w r/w r/w r/w initial value 00000000 128 8235b?avr?04/11 attiny20 trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if t he adc interrupt flag is set . 15.13.5 didr0 ? digital input disable register 0 ? bits 7:0 ? adc7d:adc0d : adc [7:0] digital input disable when a bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bi t will always read as zero when th is bit is set. when an analog signal is applied to the adc[7:0] pin and the digi tal input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 15-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 0x0d adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 129 8235b?avr?04/11 attiny20 16. spi ? serial peripheral interface 16.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 16.2 overview the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the attiny20 and peripheral devices or between several avr devices. the spi module is illustrated in figure 16-1 . figure 16-1. spi block diagram note: refer to figure 1-1 on page 2 , and table 16-1 on page 131 for spi pin placement. spi2x spi2x clkio ss divider /2/4/8/16/32/64/128 130 8235b?avr?04/11 attiny20 to enable the spi module, the prspi bit in the power reduction register must be written to zero. see ?prr ? power reduction register? on page 29 . the interconnection between master and slave cpus with spi is shown in figure 16-2 on page 130 . the system consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle wh en pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte , the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 16-2. spi master-slave interconnection the system is single buffered in the transmit di rection and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is complet ed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the minimum low and high periods should be: shift enable 131 8235b?avr?04/11 attiny20 low periods: longer than 2 cpu clock cycles. high periods: longer than 2 cpu clock cycles. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 16-1 on page 131 . for more details on automatic port overrides, refer to ?alternate port functions? on page 49 . note: see ?alternate functions of port b? on page 55 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples mu st be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 16-1. spi pin overrides pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input assembly code example spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 135 8235b?avr?04/11 attiny20 figure 16-4. spi transfer format with cpha = 1 data bits are shifted out and latched in on opposite edges of the sck signal, ensuring sufficient time for data signals to st abilize. this is shown in table 16-2 , which is a summary of table 16-3 on page 136 and table 16-4 on page 136 . 16.5 register description 16.5.1 spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi in terrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. table 16-2. spi modes spi mode conditions leading edge trailing edge 0 cpol=0, cpha=0 sample (rising) setup (falling) 1 cpol=0, cpha=1 setup (rising) sample (falling) 2 cpol=1, cpha=0 sample (falling) setup (rising) 3 cpol=1, cpha=1 setup (falling) sample (rising) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) bit 76543210 0x30 spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 136 8235b?avr?04/11 attiny20 ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will th en have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is sum- marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is summarized below: ? bits 1:0 ? spr[1:0]: spi clock rate select 1 and 0 these two bits control the sck rate of the dev ice configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the i/o clock frequency f clk_i/o is shown in the following table: table 16-3. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 16-4. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 16-5. relationship between sck and the i/o clock frequency spi2x spr1 spr0 sck frequency 000 f clk_i/o / 4 001 f clk_i/o / 16 010 f clk_i/o / 64 011 f clk_i/o / 128 100 f clk_i/o / 2 101 f clk_i/o / 8 110 f clk_i/o / 32 111 f clk_i/o / 64 137 8235b?avr?04/11 attiny20 16.5.2 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is dr iven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardwa re when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bits 5:1 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logi c one the spi speed (sck freque ncy) will be doubled when the spi is in master mode (see table 16-5 ). this means that the minimum sck period will be two i/o clock periods. when the spi is configured as sl ave, the spi is only guaranteed to work at f clk_i/o /4 or lower. 16.5.3 spdr ? spi data register the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. bit 76543210 0x2f spif wcol ? ? ? ? ? spi2x spsr read/write r/w r/w r r r r r r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x2e msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxu ndefined 138 8235b?avr?04/11 attiny20 17. twi ? two wire slave interface 17.1 features ? phillips i 2 c compatible ? smbus compatible (with reservations) ? 100 khz and 400 khz support at low system clock frequencies ? slew-rate limited output drivers ? input filter provides noise suppression ? 7-bit, and general call address recognition in hardware ? address mask register for address masking or dual address match ? 10-bit addressing supported ? optional software address recognition prov ides unlimited number of slave addresses ? slave can operate in all sleep modes, including power down ? slave arbitration allows support for smbus address resolve protocol (arp) 17.2 overview the two wire interface (twi) is a bi-directional , bus communication interface, which uses only two wires. the twi is i 2 c compatible and, with reservat ions, smbus compatible (see ?compati- bility with smbus? on page 144 ). a device connected to the bus must act as a mast er or slave.the master initiates a data transac- tion by addressing a slave on the bus, and telling whether it wants to transmit or receive data. one bus can have several masters, and an arbitration process handles priority if two or more masters try to transmit at the same time. the twi module in attiny20 implements slave func tionality, only. lost arbitration, errors, colli- sions and clock holds on the bus are detected in hardware and indicated in separate status flags. both 7-bit and general address call recognition is implemented in hardware. 10-bit addressing is also supported. a dedicated address mask regist er can act as a second address match register or as a mask register for the slave address to match on a range of addresses. the slave logic continues to operate in all sleep modes, includi ng power down. this enables the slave to wake up from sleep on twi address match. it is poss ible to disable the address matching and let this be handled in software instead. this allows the slave to detect and respond to several addresses. smart mode can be enabled to auto trigger operations and reduce software complexity. the twi module includes bus state logic that collects information to detect start and stop conditions, bus collision and bus errors. the bus state logic continues to operate in all sleep modes including power down. 17.3 general twi bus concepts the two-wire interface (twi) provides a simple tw o-wire bi-directional bu s consisting of a serial clock line (scl) and a serial data line (sda). the two lines are open collector lines (wired-and), and pull-up resistors (rp) are the only external components needed to drive the bus. the pull-up resistors will provide a high level on the lines when none of the connect ed devices are driving the bus. a constant current source can be used as an alternative to the pull-up resistors. 139 8235b?avr?04/11 attiny20 the twi bus is a simple and efficient method of interconnecting multiple devices on a serial bus. a device connected to the bus can be a master or slave, where the master controls the bus and all communication. figure 17-1 illustrates the twi bus topology. figure 17-1. twi bus topology a unique address is assigned to all slave devices connected to the bus, and the master will use this to address a slave and initiate a data transaction. 7-bit or 10-bit addressing can be used. several masters can be connected to the same bus, and this is called a multi-master environ- ment. an arbitration mechanism is provided for resolving bus ownership between masters since only one master device may own the bus at any given time. a device can contain both master and slave logic, and can emulate multiple slave devices by responding to more than one address. a master indicates the start of transaction by issuing a start condition (s) on the bus. an address packet with a slave address (address) and an indication whether the master wishes to read or write data (r/w ), is then sent. after all data packets (data) are transferred, the mas- ter issues a stop condition (p) on the bus to end the transaction. the receiver must acknowledge (a) or not-acknowledge (a ) each byte received. figure 17-2 shows a twi transaction. figure 17-2. basic twi transaction diagram topology 140 8235b?avr?04/11 attiny20 the master provides the clock signal for the tr ansaction, but a device connected to the bus is allowed to stretch the low level period of the clock to decrea se the clock speed. 17.3.1 electrical characteristics the twi follows the electrical specifications and timing of i 2 c and smbus. see ?compatibility with smbus? on page 144 . 17.3.2 start and stop conditions two unique bus conditions are used for marking the beginning (start) and end (stop) of a transaction. the master issues a start condition(s) by indicating a high to low transition on the sda line while the scl line is kept high. the master completes the transaction by issuing a stop condition (p), indicated by a low to high transition on the sda line while scl line is kept high. figure 17-3. start and stop conditions multiple start conditions can be issued during a single transaction. a start condition not directly following a stop condition, are named a repeated start condition (sr). 17.3.3 bit transfer as illustrated by figure 17-4 a bit transferred on the sda line must be stable for the entire high period of the scl line. consequently the sda value can only be changed during the low period of the clock. this is ensured in hardware by the twi module. figure 17-4. data validity combining bit transfers results in the formation of address and data packets. these packets consist of 8 data bits (one byte) with the most sign ificant bit transferred first, plus a single bit not- acknowledge (nack) or acknowledge (ack) response. the addressed device signals ack by pulling the scl line low, and nack by leaving the line scl high during the ninth clock cycle. 141 8235b?avr?04/11 attiny20 17.3.4 address packet after the start condition, a 7-bit address followed by a read/write (r/w ) bit is sent. this is always transmitted by the master. a slave reco gnizing its address will ac k the address by pull- ing the data line low the next scl cycle, while all other slaves should keep the twi lines released, and wait for the next start and address. the 7-bit address, the r/w bit and the acknowledge bit combined is the address packet. only one address packet for each start condition is given, also when 10-bit addressing is used. the r/w specifies the direction of the transaction. if the r/w bit is low, it indicates a master write transaction, and the ma ster will transmit its data afte r the slave has acknowledged its address. opposite, for a master read operation the slave will st art to transmit data after acknowledging its address. 17.3.5 data packet data packets succeed an address packet or another data packet. all data packets are nine bits long, consisting of one data byte and an acknowl edge bit. the direction bit in the previous address packet determines the direction in which the data is transferred. 17.3.6 transaction a transaction is the complete transfer from a start to a stop condition, including any repeated start conditions in between. the twi standard defines three fundamental transac- tion modes: master write, master read, and combined transaction. figure 17-5 illustrates the master write transaction. the master init iates the transaction by issu- ing a start condition (s) followed by an addr ess packet with direction bit set to zero (address+w ). figure 17-5. master write transaction given that the slave acknowledges the address, the master can start transmitting data (data) and the slave will ack or nack (a/a ) each byte. if no data packet s are to be transmitted, the master terminates the transaction by issuing a stop condition (p) directly after the address packet. there are no limitations to the number of data packets that can be transferred. if the slave signal a nack to the data, the master must assume that the slave cannot receive any more data and terminate the transaction. figure 17-6 illustrates the master read tr ansaction. the master initia tes the transacti on by issu- ing a start condition followed by an address packet with direct ion bit set to one (adress+r). the addressed slave must acknowledge the address for the master to be allowed to continue the transaction. 142 8235b?avr?04/11 attiny20 figure 17-6. master read transaction given that the slave acknowledges the address, the master can start receiving data from the slave. there are no limitations to the number of data packets that can be transferred. the slave transmits the data while the master signals ack or nack after each data byte. the master ter- minates the transfer with a nack before issuing a stop condition. figure 17-7 illustrates a co mbined transaction. a combined transaction consists of several read and write transactions separated by a repeated start conditions (sr). figure 17-7. combined transaction 17.3.7 clock and clock stretching all devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock frequency or to insert wait states while processing data. a device that needs to stretch the clock can do this by holding/forcing th e scl line low after it de tects a low level on the line. three types of clock stretching can be defined as shown in figure 17-8 . figure 17-8. clock stretching if the device is in a sleep mode and a start co ndition is detected the clock is stretched during the wake-up period for the device. a slave device can slow down the bus frequency by stretching the clock periodically on a bit level. this allows the slave to run at a lower system clock frequency. however, the overall per- formance of the bus will be reduced accordin gly. both the master and slave device can randomly stretch the clock on a byte level basis before and after the ack/nack bit. this pro- vides time to process incoming or prepare outgoing data, or performing other time critical tasks. 143 8235b?avr?04/11 attiny20 in the case where the slave is stre tching the clock the master will be forced into a wait-state until the slave is ready and vice versa. 17.3.8 arbitration a master can only start a bus transaction if it has detected that the bus is idle. as the twi bus is a multi master bus, it is possible that two devices initiate a transaction at the same time. this results in multiple masters owni ng the bus simultaneously. this is solved using an arbitration scheme where the master lo ses control of the bus if it is not able to trans mit a high level on the sda line. the masters who lose arbitration must then wait until the bus becomes idle (i.e. wait for a stop condition) before attempting to reacquire bus ownership. slave devices are not involved in the arbitration procedure. figure 17-9. twi arbitration figure 17-9 shows an example where two twi masters are contending for bus ownership. both devices are able to issue a start condition, but device1 loses arbitration when attempting to transmit a high level (bit 5) while device2 is transmitting a low level. arbitration between a repeated start condition and a data bit, a stop condition and a data bit, or a repeated start conditi on and stop condition are not allowed and will require special handling by software. 17.3.9 synchronization a clock synchronization algorithm is necessary fo r solving situations where more than one mas- ter is trying to control the scl line at the same time. the algorithm is based on the same principles used for clock stretching previously described. figure 17-10 shows an example where two masters are competing for the control over the bus clock. the scl line is the wired-and result of the two ma sters clock outputs. 144 8235b?avr?04/11 attiny20 figure 17-10. clock synchronization a high to low transition on the scl line will force the line low for all masters on the bus and they start timing their low clock period. the timing length of the low clock period can vary between the masters. when a master (device1 in this case) has completed its low period it releases the scl line. however, the scl line will not go high before all masters have released it. conse- quently the scl line will be held low by the de vice with the longest low period (device2). devices with shorter low periods must insert a wa it-state until the clock is released. all masters start their high period when the scl line is released by all devices and has become high. the device which first completes it s high period (device1) forces the clock line low and the proce- dure are then repeated. the result of this is that the device with the shortest clock period determines the high period while the low period of the clock is determined by the longest clock period. 17.3.10 compatibility with smbus as with any other i 2 c-compliant interface there are know n compatibility issues the designer should be aware of before connecting a twi de vice to smbus devices. for use in smbus envi- ronments, the following should be noted: ? all i/o pins of an avr, including those of the two-wire interface, have protection diodes to both supply voltage and ground. see figure 10-1 on page 44 . this is in contradiction to the requirements of the smbus specifications. as a result, supply voltage mustn?t be removed from the avr or the protection diodes will pu ll the bus lines down. power down and sleep modes is not a problem, provided supply voltages remain. ? the data hold time of the twi is lower than specified for smbus. the twshe bit of twscra can be used to increase the hold time. see ?twscra ? twi slave control register a? on page 146 . ? smbus has a low speed limit, while i 2 c hasn?t. as a master in an smbus environment, the avr must make sure bus speed does not drop below specifications, since lower bus speeds trigger timeouts in smbus slaves. if the avr is configured a slave there is a possibility of a bus lockup, since the twi module doesn't identify timeouts. 17.4 twi slave operation the twi slave is byte-oriented with optional interrupts after each byte. there are separate inter- rupt flags for data interrupt and address/stop interrupt. interrupt flags can be set to trigger the 145 8235b?avr?04/11 attiny20 twi interrupt, or be used for polled operation. there are dedicated status flags for indicating ack/nack received, clock hold, collisi on, bus error and re ad/write direction. when an interrup t flag is set, the scl line is forced lo w. this will give the slave time to respond or handle any data, and will in most cases require software interaction. figure 17-11 . shows the twi slave operation. the diamond shapes symbols (sw) indicate where software interaction is required. figure 17-11. twi slave operation the number of interrupts generated is kept at a minimum by automatic handling of most condi- tions. quick command can be enabled to auto trigger operations and reduce software complexity. promiscuous mode can be enabled to allow the slave to respond to all received addresses. 17.4.1 receiving address packets when the twi slave is properly configured, it will wait for a start condition to be detected. when this happens, the successi ve address byte will be receiv ed and checked by the address match logic, and the slave will ack the correct address. if the received address is not a match, the slave will not acknowledge the address and wait for a new start condition. the slave address/stop interrupt flag is set when a start condition succeeded by a valid address packet is detected. a general call address will al so set the interrupt flag. a start condition immediately followed by a st op condition, is an illegal operation and the bus error flag is set. the r/w direction flag reflects the direction bit received with the address. this can be read by software to determine the type of operation currently in progress. depending on the r/w direction bit and bus condition one of four distinct cases (1 to 4) arises following the address packet. the different cases must be handled in software. 17.4.1.1 case 1: address packet accepted - direction bit set if the r/w direction flag is set, this indicates a master read operation. the scl line is forced low, stretching the bus clock. if ack is sent by the slave, the slave hardware will set the data interrupt flag indicating data is needed for transmit . if nack is sent by the slave, the slave will wait for a new start condition and address match. 146 8235b?avr?04/11 attiny20 17.4.1.2 case 2: address packet accepted - direction bit cleared if the r/w direction flag is cleared this indicates a master write operation. the scl line is forced low, stretching the bus clock. if ack is sent by the slave, the slave will wait for data to be received. data, repeated start or stop can be received after this. if nack is indicated the slave will wait for a new start condition and address match. 17.4.1.3 case 3: collision if the slave is not able to send a high level or na ck, the collision flag is set and it will disable the data and acknowledge output from the slave logi c. the clock hold is released. a start or repeated star t condition will be accepted. 17.4.1.4 case 4: stop condition received. operation is the same as case 1 or 2 above with one exception. when the stop condition is received, the slave address/stop flag will be set indicating that a stop condition and not an address match occurred. 17.4.2 receiving data packets the slave will know when an address packet with r/w direction bit cleared has been success- fully received. after acknowledging this, the slave must be ready to receive data. when a data packet is received the data interrupt flag is set, and the slave must indicate ack or nack. after indicating a nack, the slave must expect a stop or repeated start condition. 17.4.3 transmitting data packets the slave will know when an address packet, with r/w direction bit set, has been successfully received. it can then start sending data by writing to the slave data register. when a data packet transmission is completed, the data interrupt flag is set. if the master indicates nack, the slave must stop transmitting data, and expect a stop or repeated start condition. 17.5 register description 17.5.1 twscra ? twi slave control register a ? bit 7 ? twshe: twi sda hold time enable when this bit is set each negative transition of scl triggers an additional internal delay, before the device is allowed to change the sda line. the added delay is approximately 50ns in length. this may be useful in smbus systems. ? bit 6 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 5 ? twdie: twi data interrupt enable when this bit is set and interr upts are enabled, a twi interrup t will be generated when the data interrupt flag (twdif) in twssra is set. bit 76543210 0x2d twshe ? twdie twasie twen twsie twpme twsme twscra read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 147 8235b?avr?04/11 attiny20 ? bit 4 ? twasie: twi address/stop interrupt enable when this bit is se t and interrupts ar e enabled, a twi interrup t will be generated when the address/stop interrupt flag (twasif) in twssra is set. ? bit 3 ? twen: two-wire interface enable when this bit is set the slave two-wire interface is enabled. ? bit 2 ? twsie: twi stop interrupt enable setting the stop interrupt enable (twsie) bit will set the twasif in the twssra register when a stop condition is detected. ? bit 1 ? twpme: twi promiscuous mode enable when this bit is set the address match logic of the slave twi responds to all received addresses. when this bit is cleared the address match logi c uses the twsa register to determine which address to recognize as its own. ? bit 0 ? twsme: twi smart mode enable when this bit is set the twi slave enters smart mode, where the acknowledge action is sent immediately after the twi data register (twsd) has been read. acknowledge action is defined by the twaa bit in twscrb. when this bit is cleared the acknowledge action is sent after twcmdn bits in twscrb are written to 1x. 17.5.2 twscrb ? twi slave control register b ? bits 7:3 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 2 ? twaa: twi acknowledge action this bit defines the slave's acknowledge behavior after an address or data byte has been received from the master. depending on the twsme bit in twscra the acknowledge action is executed either when a valid command has been written to twcmdn bits, or when the data reg- ister has been read. acknowledge action is also executed if clearing twaif flag after address match or twdif flag during master transmit. see table 17-1 for details. bit 76543210 0x2c ? ? ? ? ? twaa twcmd1 twcmd0 twscrb read/write rrrrrr/www initial value 0 0 0 0 0 0 0 0 table 17-1. acknowledge action of twi slave twaa action twsme when 0 send ack 0 when twcmdn bits are written to 10 or 11 1 when twsd is read 1 send nack 0 when twcmdn bits are written to 10 or 11 1 when twsd is read 148 8235b?avr?04/11 attiny20 ? bits 1:0 ? twcmd[1:0]: twi command writing these bits triggers the slave operation as defined by table 17-2 on page 148 . the type of operation depends on the twi slave interrupt flags, twdif and twasif. the acknowledge action is only executed when the slave receives data bytes or address byte from the master. writing the twcmd bits will automatically re lease the scl line and clear the twch and slave interrupt flags. twaa and twcmdn bits can be wr itten at the same time. ackn owledge action will then be exe- cuted before the command is triggered. the twcmdn bits are strobed and always read zero. 17.5.3 twssra ? twi slave status register a ? bit 7 ? twdif: twi data interrupt flag this flag is set when a data byte has been succe ssfully received, i.e. no bus errors or collisions have occurred during the operation. when this fl ag is set the slave forces the scl line low, stretching the twi clock period. the scl line is released by clearing the interrupt flags. writing a one to this bit will clear the flag. this flag is also aut omatically cleared when writing a valid command to the twcmdn bits in twscrb. ? bit 6 ? twasif: twi address/stop interrupt flag this flag is set when the slave detects that a valid address has been received, or when a trans- mit collision has been detected. when this flag is set the slave forces the scl line low, stretching the twi clock period. the scl line is released by clearing the interrupt flags. table 17-2. twi slave command twcmd[1:0] twdir operation 00 x no action 01 x reserved 10 used to comple te transaction 0 execute acknowledge action, then wait for any start (s/sr) condition 1 wait for any start (s/sr) condition 11 used in response to an ad dress byte (twasif is set) 0 execute acknowledge action, then receive next byte 1 execute acknowledge action, then set twdif used in response to a da ta byte (twdif is set) 0 execute acknowledge action, then wait for next byte 1 no action bit 76543210 0x2b twdif twasif twch twra twc twbe twdir twas twssra read/write r/w r/w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 149 8235b?avr?04/11 attiny20 if twasie in twscra is set, a stop condition on the bus will also set twasif. stop condi- tion will set the flag only if system clock is fast er than the minimum bus free time between stop and start. writing a one to this bit will clear the flag. this flag is also aut omatically cleared when writing a valid command to the twcmdn bits in twscrb. ? bit 5 ? twch: twi clock hold this bit is set when the slave is holding the scl line low. this bit is read-only, and set when twdif or tw asif is set. the bit can be cleared indirectly by clearing the interrupt flags and releasing the scl line. ? bit 4 ? twra: twi receive acknowledge this bit contains the most recently received acknowledge bit from the master. this bit is read-only. when zero, the most recent acknowledge bit from the maser was ack and, when one, the most recent acknowledge bit was nack. ? bit 3 ? twc: twi collision this bit is set when the slave was not able to tr ansfer a high data bit or a nack bit. when a col- lision is detected, the slav e will commence its normal operation, and disable data and acknowledge output. no low values are shifted out onto the sda line. this bit is cleared by writing a one to it. the bi t is also cleared automatically when a start or repeated start condition is detected. 150 8235b?avr?04/11 attiny20 ? bit 2 ? twbe: twi bus error this bit is set when an illegal bus condition has occur ed during a transfer. an illegal bus condi- tion occurs if a repeated start or stop condition is detected, and the number of bits from the previous start condition is not a multiple of nine. this bit is cleared by writing a one to it. for bus errors to be detected, the system clock frequency must be at least four times the scl frequency. ? bit 1 ? twdir: twi read/write direction this bit indicates the direction bit from the last address packet received from a master. when this bit is one, a master read operation is in progress. when the bit is zero a master write opera- tion is in progress. ? bit 0 ? twas: twi address or stop this bit indicates why the twasif bit was last set. if zero, a stop condition caused twasif to be set. if one, address detection caused twasif to be set. 17.5.4 twsa ? twi slave address register the slave address register contains the twi slave address used by the slave address match logic to determine if a master has addressed the slave. when using 7-bit or 10-bit address rec- ognition mode, the high seven bits of the address register (twsa[7:1]) represent the slave address. the least significant bit (twsa0) is used for general call address recognition. setting twsa0 enables general call address recognition logic. when using 10-bit addressing the address match logic only support hardware address recogni- tion of the first byte of a 10 -bit address. if twsa[7:1] is se t to "0b11110nn", 'n n' will represent bits 9 and 8 of the slave address. the next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. when the address match logic detects that a valid address byte has been received, the twasif is set and the twdir flag is updated. if twpme in twscra is set, the address match logic responds to all addresses transmitted on the twi bus. twsa is not used in this mode. 17.5.5 twsd ? twi slave data register the data register is used when transmitting and received data. during transfer, data is shifted from/to the twsd register and to/from the bus. therefore, the data register cannot be accessed during byte transfers. this is protected in hardware. the data register can only be accessed when the scl line is held low by the slave, i.e. when twch is set. bit 76543210 0x2a twsa[7:0] twsa read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x28 twsd[7:0] twsd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 151 8235b?avr?04/11 attiny20 when a master reads data from a slave, the data to be sent must be written to the twsd regis- ter. the byte transfer is started when the master starts to clock the data byte from the slave. it is followed by the slave receiving the acknowledge bit from the master. the twdif and the twch bits are then set. when a master writes data to a slave, the twdif and the twch flags are set when one byte has been received in the data register. if smart mode is enabled, reading the data register will trigger the bus operation, as set by the twaa bit in twscrb. accessing twsd in smart mode will clear the slave da ta interrupt flag and the twch bit. 17.5.6 twsam ? twi slave address mask register ? bits 7:1 ? twsam[7:1]: twi address mask these bits can act as a second address match r egister, or an address mask register, depending on the twae setting. if twae is set to zero, twsam can be loaded with a 7-bit slave address mask. each bit in twsam can mask (disable) the corresponding addr ess bit in the twsa register. if the mask bit is one the address match between the incoming address bit and the corresponding bit in twsa is ignored. in ot her words, masked bits will always match. if twae is set to one, twsam can be loaded with a second slave address in addition to the twsa register. in this mode, the slave will match on 2 unique addresses, one in twsa and the other in twsam. ? bit 0 ? twae: twi address enable by default, this bit is zero and the twsam bits acts as an address mask to the twsa register. if this bit is set to one, the slave address match logic responds to the two unique addresses in twsa and twsam. bit 76543210 0x29 twsam[7:1] twae twsam read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 152 8235b?avr?04/11 attiny20 18. programming interface 18.1 features ? physical layer: ? synchronous data transfer ? bi-directional, half-duplex receiver and transmitter ? fixed frame format with one start bit, 8 data bits, one parity bit and 2 stop bits ? parity error detection, frame error detection and break character detection ? parity generation and collision detection ? automatic guard time insertion betw een data reception and transmission ? access layer: ? communication based on messages ? automatic exception handling mechanism ? compact instruction set ? nvm programming access control ? tiny programming interface control and status space access control ? data space access control 18.2 overview the tiny programming interface (tpi) supports external programming of all non-volatile memo- ries (nvm). memory programming is done via th e nvm controller, by executing nvm controller commands as described in ?memory programming? on page 163 . the tiny programming interface (tpi) provides a ccess to the programming facilities. the inter- face consists of two layers: th e access layer and the physical la yer. the layers are illustrated in figure 18-1 . figure 18-1. the tiny programming interface and related internal interfaces programming is done via the phys ical interface. this is a 3-pi n interface, whic h uses the reset pin as enable, the tpiclk pin as the clock inpu t, and the tpidata pin as data input and output. nvm can be programmed at 5v, only. 18.3 physical layer of ti ny programming interface the tpi physical layer handles th e basic low-level serial communic ation. the tpi physical layer uses a bi-directional, half-duplex serial receiver and transmitter. the physical layer includes serial-to-parallel and parallel-to-serial data conversion, start-of-frame detection, frame error detection, parity error detection, pa rity generation and collision detection. access layer physical layer nvm controller non-volatile memories tpiclk reset t pidata tiny programming interface (tpi) data bus 153 8235b?avr?04/11 attiny20 the tpi is accessed via three pins, as follows: reset : tiny programming interface enable input tpiclk: tiny programming interface clock input tpidata: tiny programming interface data input/output in addition, the v cc and gnd pins must be connected between the external programmer and the device. 18.3.1 enabling the following sequence enables the tiny programming interface: ? apply 5v between v cc and gnd ? depending on the method of reset to be used: ? either: wait t tout (see table 20-4 on page 175 ) and then set the reset pin low. this will reset the device and enable the tpi physical layer. the reset pin must then be kept low for the entire programming session ? or: if the rstdisbl configuration bit has been programmed, apply 12v to the reset pin. the reset pin must be kept at 12v for the entire programming session ?wait t rst (see table 20-4 on page 175 ) ? keep the tpidata pin high for 16 tpiclk cycles see figure 18-2 for guidance. figure 18-2. sequence for enabling the tiny programming interface 18.3.2 disabling provided that the nvm enable bit has been clear ed, the tpi is automatically disabled if the reset pin is released to inactive high state or, alternatively, if v hv is no longer applied to the reset pin. if the nvm enable bit is not cleared a power down is required to exit tpi programming mode. see nvmen bit in ?tpisr ? tiny programming interface status register? on page 162 . 18.3.3 frame format the tpi physical layer supports a fixed frame fo rmat. a frame consists of one character, eight bits in length, and one start bit, a parity bit and two stop bits. data is transferred with the least significant bit first. reset t rst tpidata tpiclk 16 x tpiclk cycles 154 8235b?avr?04/11 attiny20 figure 18-3. serial frame format. symbols used in figure 18-3 : st: start bit (always low) d0-d7: data bits (least significant bit sent first) p: parity bit (using even parity) sp1: stop bit 1 (always high) sp2: stop bit 2 (always high) 18.3.4 parity bit calculation the parity bit is always calculated using even parit y. the value of the bit is calculated by doing an exclusive-or of all the data bits, as follows: p = d0 ? d1 ? d2 ? d3 ? d4 ? d5 ? d6 ? d7 ? 0 where: p: parity bit using even parity d0-d7: data bits of the character 18.3.5 supported characters the break character is equa l to a 12 bit long low level. it c an be extended be yond a bit-length of 12. the idle character is equal to a 12 bit long high level. it can be extended beyond a bit-length of 12. figure 18-4. supported characters. 18.3.6 operation the tpi physical layer operates synchronously on the tpiclk provided by the external pro- grammer. the dependency between the clock edges and data sampling or data change is shown in figure 18-5 . data is changed at falling edge s and sampled at rising edges. tpidata tpiclk sp1 st sp2 idle/st idle p d1 d0 d7 idle/st idle break character data character sp1 st sp2 idle/st idle p d1 d0 d7 tpidata idle/st idle idle character tpidata tpidata 155 8235b?avr?04/11 attiny20 figure 18-5. data changing and data sampling. the tpi physical layer supports two modes of operation: transmit and receive. by default, the layer is in receive mode, waiting for a start bit. the mode of operation is controlled by the access layer. 18.3.7 serial data reception when the tpi physical layer is in receive mode, dat a reception is started as soon as a start bit has been detected. each bit that follows the start bit will be samp led at the rising edge of the tpiclk and shifted into the shift register until the second stop bit has been received. when the complete frame is present in the shift register the rece ived data will be available for the tpi access layer. there are three possible exceptions in the receive mode: frame error, parity error and break detection. all these exceptions are signalized to the tpi access layer, which then enters the error state and puts the tpi physical layer into receive mode, waiting for a break character. ? frame error exception. the frame error exception indicates the state of the stop bit. the frame error exception is set if the stop bit was read as zero. ? parity error exception. the parity of the data bits is calculated during the frame reception. after the frame is received completely, the result is compared with the parity bit of the frame. if the comparison fails the parity error exception is signalized. ? break detection exception. the break detection exception is given when a complete frame of all zeros has been received. 18.3.8 serial data transmission when the tpi physical layer is ready to send a new frame it initiates data transmission by load- ing the shift register with the data to be transmitted. when the shift register has been loaded with new data, the transmitter shifts one complete frame out on the tpidata line at the transfer rate given by tpiclk. if a collision is detected during tr ansmission, the output driver is disabled. the tpi access layer enters the error state and the tpi physical layer is put into receive mode, waiting for a break character. 18.3.9 collision detection exception the tpi physical layer uses one bi-directional data line for both data reception and transmission. a possible drive contention may occur, if the external programmer and the tpi physical layer drive the tpidata line simultaneously. in order to reduce the effect of the drive contention, a collision detection mechanism is supported. the collision detecti on is based on the way the tpi physical layer drives the tpidata line. tpidata tpiclk sample setup 156 8235b?avr?04/11 attiny20 the tpidata line is driven by a tri-state, push-pull driver with internal pull-up. the output driver is always enabled when a logical zero is sent. when sending successive logical ones, the output is only driven actively during the first clock cycle. after this, the output driver is automatically tri- stated and the tpidata line is kept high by the internal pull-up. the output is re-enabled, when the next logical zero is sent. the collision detection is enabled in transmit mode, when the output driver has been disabled. the data line should now be kept high by the internal pull-up and it is monitored to see, if it is driven low by the ex ternal programmer. if the output is read low, a co llision has been detected. there are some potential pi t-falls related to the way collision detection is perf ormed. for exam- ple, collisions cannot be detecte d when the tpi physical laye r transmits a bit-stream of successive logical zeros, or bit-stream of alternating logical ones and zeros. this is because the output driver is active all the time, preventing polling of the tp idata line. however, within a sin- gle frame the two stop bits should always be transmitted as logical ones, enabling collision detection at least once per frame (as long as the frame format is not violated regarding the stop bits). the tpi physical layer will cease transmission w hen it detects a collision on the tpidata line. the collision is signalized to the tpi access la yer, which immediately ch anges the physical layer to receive mode and goes to the error state. the tpi access layer can be recovered from the error state only by sending a break character. 18.3.10 direction change in order to ensure correct timing of the half-duplex operation, a simple guard time mechanism has been added to the physical layer. when t he tpi physical layer changes from receive to transmit mode, a configurable num ber of additional idle bits are inserted before the start bit is transmitted. the minimum transition time between receive and transmit mode is two idle bits. the total idle time is the specifie d guard time plus two idle bits. the guard time is configured by dedicated bits in the tpipcr register. the default guard time value after the physical layer is initialized is 128 bits. the external programmer looses control of the tpidata line when the tpi target changes from receive mode to transmit. the guard time feature relaxes this critical phase of the communica- tion. when the external programmer changes from receive mode to transmit, a minimum of one idle bit should be inserted before the start bit is transmitted. 18.4 access layer of tiny programming interface the tpi access layer is respons ible for handling the communication with the external program- mer. the communication is based on a message format, where each message comprises an instruction followed by one or more byte-sized operands. the instruction is always sent by the external programmer but operands are sent either by the external programmer or by the tpi access layer, depending on the type of instruction issued. the tpi access layer controls the character transf er direction on the tpi physical layer. it also handles the recovery from the error state after exception. the control and status space (css) of the tiny programming interface is allocated for control and status registers in the tpi access layer. th e css consist of registers directly involved in the operation of the tpi itself. these register are accessible using the sldcs and sstcs instructions. 157 8235b?avr?04/11 attiny20 the access layer can also access the data space, either directly or indirectly using the pointer register (pr) as the address pointer. the data space is accessible using the sld, sst, sin and sout instructions. the address pointer can be stored in the pointer register using the sldpr instruction. 18.4.1 message format each message comprises an instruction followed by one or more byte operands. the instruction is always sent by the external programmer. depending on the instruction all the following oper- ands are sent either by the external programmer or by the tpi. the messages can be categorized in two types based on the instruction, as follows: ? write messages. a write message is a request to write data. the write message is sent entirely by the external programmer. this message type is used with the sstcs, sst, stpr, sout and skey instructions. ? read messages. a read message is a request to read data. the tpi reacts to the request by sending the byte operands. this message type is used with the sldcs, sld and sin instructions. all the instructions except the skey instruction require the instru ction to be followed by one byte operand. the skey instruction requires 8 byte operands. for more information, see the tpi instruction set on page 157 . 18.4.2 exception handling and synchronisation several situations are considered exceptions from normal operation of the tpi. when the tpi physical layer is in receive mode, these exceptions are: ? the tpi physical layer detects a parity error. ? the tpi physical layer detects a frame error. ? the tpi physical layer recognizes a break character. when the tpi physical layer is in tr ansmit mode, the possible exceptions are: ? the tpi physical layer detects a data collision. all these exceptions are signalized to the tpi access layer. the access layer responds to an exception by aborting any on-g oing operation and enters the erro r state. the ac cess layer will stay in the error state until a break character has been received, after whic h it is taken back to its default state. as a consequence, the extern al programmer can always synchronize the proto- col by simply transmitting two successive break characters. 18.5 instruction set the tpi has a compact instruction set that is us ed to access the tpi control and status space (css) and the data space. the instructions allo w the external programmer to access the tpi, the nvm controller and the nvm me mories. all instructions exce pt skey require one byte oper- and following the inst ruction. the skey instructio n is followed by 8 data bytes. all instructions are byte-sized. 158 8235b?avr?04/11 attiny20 the tpi instruction se t is summarised in table 18-1 . 18.5.1 sld - serial load from data space using indirect addressing the sld instruction uses indirect addressing to load data from the data space to the tpi physi- cal layer shift-register for serial read-out. the data space location is pointed by the pointer register (pr), where the address must have been stored before data is accessed. the pointer register can either be left unchanged by the operation, or it can be post-incremented, as shown in table 18-2 . 18.5.2 sst - serial store to data space using indirect addressing the sst instruction uses indirect addressing to stor e into data space the byte that is shifted into the physical layer shift register. the data space lo cation is pointed by the pointer register (pr), where the address must have been stored before the operation. the pointer register can be either left unchanged by the operation, or it can be post-incremented, as shown in table 18-3 . table 18-1. instruction set summary mnemonic operand description operation sld data, pr serial load from data space using indirect addressing data ds[pr] sld data, pr+ serial load from data space using indirect addressing and post-increment data ds[pr] pr pr+1 sst pr, data serial store to data space using indirect addressing ds[pr] data sst pr+, data serial store to data space using indirect addressing and post-increment ds[pr] data pr pr+1 sstpr pr, a serial store to pointer register using direct addressing pr[a] data sin data, a serial in from data space data i/o[a] sout a, data serial ou t to data space i/o[a] data sldcs data, a serial load from control and status space using direct addressing data css[a] sstcs a, data serial store to control and status space using direct addressing css[a] data skey key, {8{data}} serial key key {8{data}} table 18-2. the serial load from data space (sld) instruction operation opcode remarks register data ds[pr] 0010 0000 pr pr unchanged data ds[pr] 0010 0100 pr pr + 1 post increment table 18-3. the serial store to data space (sld) instruction operation opcode remarks register ds[pr] data 0110 0000 pr pr unchanged ds[pr] data 0110 0100 pr pr + 1 post increment 159 8235b?avr?04/11 attiny20 18.5.3 sstpr - serial store to pointer register the sstpr instruction stores the data byte that is shifted into the physical layer shift register to the pointer register (pr). the address bit of the instruction specifies which byte of the pointer register is accessed, as shown in table 18-4 . 18.5.4 sin - serial in from i/o space using direct addressing the sin instruction loads data byte from the i/o space to the shift register of the physical layer for serial read-out. the instuction uses dire ct addressing, the address consisting of the 6 address bits of the instruction, as shown in table 18-5 . 18.5.5 sout - serial out to i/o space using direct addressing the sout instruction stores the data byte that is shifted into the physical layer shift register to the i/o space. the instruction uses direct addr essing, the address consisting of the 6 address bits of the instruction, as shown in table 18-6 . 18.5.6 sldcs - serial load data from control and status space using direct addressing the sldcs instruction loads data byte from the tpi control and status space to the tpi physi- cal layer shift register for serial read-out. the sldcs instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction, as shown in table 18-7 . 18.5.7 sstcs - serial store data to control and status space using direct addressing the sstcs instruction stores the data byte that is shifted into the tpi physical layer shift regis- ter to the tpi control and status space. the sstcs instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction, as shown in table 18-8 . table 18-4. the serial store to pointer register (sstpr) instruction operation opcode remarks pr[a] data 0110 100a bit ?a? addresses pointer register byte table 18-5. the serial in from i/o space (sin) instruction operation opcode remarks data i/o[a] 0aa1 aaaa bits marked ?a? form the direct, 6-bit addres table 18-6. the serial out to i/o space (sout) instruction operation opcode remarks i/o[a] data 1aa1 aaaa bits marked ?a? form the direct, 6-bit addres table 18-7. the serial load data from control and status space (sldcs) instruction operation opcode remarks data css[a] 1000 aaaa bits marked ?a? form the direct, 4-bit addres table 18-8. the serial store data to control and status space (sstcs) instruction operation opcode remarks css[a] data 1100 aaaa bits marked ?a? form the direct, 4-bit addres 160 8235b?avr?04/11 attiny20 18.5.8 skey - serial key signaling the skey instruction is used to signal the activation key that enables nvm programming. the skey instruction is followed by the 8 data bytes that includes the activation key, as shown in table 18-9 . 18.6 accessing the non-volati le memory controller by default, nvm programming is not enabled. in order to access the nvm controller and be able to program the non-volatile memories, a unique ke y must be sent using the skey instruction. the 64-bit key that will enable nv m programming is given in table 18-10 . after the key has been given, the non-volatile memory enable (nvmen) bit in the tpi status register (tpisr) must be polled until the non-volatile memory has been enabled. nvm programming is disabled by writing a logical zero to the nvmen bit in tpisr. 18.7 control and status space regist er descriptions the control and status registers of the tiny programming interface are mapped in the control and status space (css) of the interface. these registers are not part of the i/o register map and are accessible via sldcs and sstcs instruct ions, only. the control and status registers are directly involved in configuration and status monitoring of the tpi. a summary of css registers is shown in table 18-11 . table 18-9. the serial key signalin g (skey) instruction operation opcode remarks key {8[data}} 1110 0000 data bytes follow after instruction table 18-10. enable key for non-volat ile memory programming key value nvm program enable 0x1289ab45cdd888ff table 18-11. summary of control and status registers addr. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0f tpiir tiny programming interface identification code 0x0e reserved ? ? ? ? ? ? ? ? 0x0d reserved ? ? ? ? ? ? ? ? 0x0c reserved ? ? ? ? ? ? ? ? 0x0b reserved ? ? ? ? ? ? ? ? 0x0a reserved ? ? ? ? ? ? ? ? 0x09 reserved ? ? ? ? ? ? ? ? 0x08 reserved ? ? ? ? ? ? ? ? 0x07 reserved ? ? ? ? ? ? ? ? 0x06 reserved ? ? ? ? ? ? ? ? 0x05 reserved ? ? ? ? ? ? ? ? 0x04 reserved ? ? ? ? ? ? ? ? 0x03 reserved ? ? ? ? ? ? ? ? 161 8235b?avr?04/11 attiny20 18.7.1 tpiir ? tiny programming interface identification register ? bits 7:0 ? tpiic: tiny programming interface identification code these bits give the identification code for the tiny programming interface. the code can be used be the external programmer to identify the tpi. the identification code of the tiny pro- gramming interface is shown in table 18-12 . 18.7.2 tpipcr ? tiny programming interface physical layer control register ? bits 7:3 ? res: reserved bits these bits are reserved and will always read as zero. ? bits 2:0 ? gt[2:0]: guard time these bits specify the number of additional idle bits that are inserted to the idle time when changing from reception mode to transmission mode. additional delays are not inserted when changing from transmission mode to reception. the total idle time when changing from reception to transmission mode is guard time plus two idle bits. table 18-13 shows the available guard time settings. 0x02 tpipcr ? ? ? ? ? gt2 gt1 gt0 0x01 reserved ? ? ? ? ? ? ? ? 0x00 tpisr ? ? ? ? ? ? nvmen ? table 18-11. summary of control and status registers (continued) addr. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 76543210 css: 0x0f programming interface identification code tpiir read/writerrrrrrrr initial value00000000 table 18-12. identification code for tiny programming interface code value interface identification 0x80 bit 76543210 css: 0x02 ? ? ? ? ? gt2 gt1 gt0 tpipcr read/writerrrrrr/wr/wr/w initial value00000000 table 18-13. guard time settings gt2 gt1 gt0 guard time (number of idle bits) 0 0 0 +128 (default value) 001+64 010+32 011+16 100+8 162 8235b?avr?04/11 attiny20 the default guard time is 128 idle bits. to speed up the communication, the guard time should be set to the shortest safe value. 18.7.3 tpisr ? tiny programming interface status register ? bits 7:2, 0 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 1 ? nvmen: non-volatile memory programming enabled nvm programming is enabled when this bit is set. the external programmer can poll this bit to verify the interface has been successfully enabled. nvm programming is disabled by writing this bit to zero. 101+4 110+2 111+0 table 18-13. guard time settings gt2 gt1 gt0 guard time (number of idle bits) bit 76543210 css: 0x00 ? ? ? ? ? ?nvmen ?tpipcr read/writerrrrrrr/wr initial value00000000 163 8235b?avr?04/11 attiny20 19. memory programming 19.1 features ? two embedded non-volatile memories: ? non-volatile memory lock bits (nvm lock bits) ?flash memory ? four separate sections inside flash memory: ? code section (program memory) ? signature section ? configuration section ? calibration section ? read access to all non-volatile me mories from application software ? read and write access to non-volatile memories from external programmer: ? read access to all non-volatile memories ? write access to nvm lock bits, flash code section and flash co nfiguration section ? external programming: ? support for in-system and mass production programming ? programming through the tiny programming interface (tpi) ? high security wi th nvm lock bits 19.2 overview the non-volatile memory (nvm) controller mana ges all access to the no n-volatile memories. the nvm controller controls all nvm timing and access privileges, and holds the status of the nvm. during normal execution the cpu will execute code from the code section of the flash memory (program memory). when entering sleep and no programming operations are active, the flash memory is disabled to minimize power consumption. all nvm are mapped to the data memory. application software can read the nvm from the mapped locations of data memory using load instruction with indirect addressing. the nvm has only one read port and, therefore, the next instruction and the data can not be read simultaneously. when the application reads data from nvm locations mapped to the data space, the data is read first before the next instruction is fetched. the cpu execution is here delayed by one system clock cycle. internal programming operations to nvm have been disabled and the nvm therefore appears to the application software as read-only. internal write or erase operations of the nvm will not be successful. the method used by the external programmer for wr iting the non-volatile memories is referred to as external pr ogramming. external progra mming can be done both in -system or in mass pro- duction. the external programmer can read and program the nvm via the tiny programming interface (tpi). in the external programming mode all nvm can be read and programmed, except the signature and the calibration sections which are read-only. nvm can be programmed at 5v, only. see table 20-9 on page 178 . 164 8235b?avr?04/11 attiny20 19.3 non-volatile memories the attiny20 has the following, embedded nvm: ? non-volatile memory lock bits ? flash memory with four separate sections 19.3.1 non-volatile memory lock bits the attiny20 provides two lock bits, as shown in table 19-1 . the lock bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the addi- tional security shown in table 19-2 . lock bits can be erased to "1" with the chip erase command, only. notes: 1. program the configuration section bits before programming nvlb1 and nvlb2. 2. "1" means unprogrammed, "0" means programmed table 19-1. lock bit byte lock bit bit no description default value 7 1 (unprogrammed) 6 1 (unprogrammed) 5 1 (unprogrammed) 4 1 (unprogrammed) 3 1 (unprogrammed) 2 1 (unprogrammed) nvlb2 1 non-volatile lock bit 1 (unprogrammed) nvlb1 0 non-volatile lock bit 1 (unprogrammed) table 19-2. lock bit protection modes memory lock bits (1) protection type lock mode nvlb2 (2) nvlb1 (2) 1 1 1 no memory lock feature enabled 210 further programming of the flash memory is disabled in the external programming mode. the configuration section bits are locked in the external programming mode 300 further programming and verification of the flash is disabled in the external programming mode. the configuration section bits are locked in the external programming mode 165 8235b?avr?04/11 attiny20 19.3.2 flash memory the embedded flash memory of attiny20 has four separate sections, as shown in table 19-3 . notes: 1. this section is read-only. 19.3.3 configuration section attiny20 has one configuration byte, which resides in the configuration section. see table 19-4 . table 19-5 briefly describes the functionality of all configuration bits and how they are mapped into the configuration byte. notes: 1. see table 20-6 on page 176 for bodlevel fuse decoding. configuration bits are not affected by a chip er ase but they can be cleared using the configura- tion section erase command (see ?erasing the configuration section? on page 169 ). note that configuration bits are locked if non-volatile lock bit 1 (nvlb1) is programmed. table 19-3. number of words and pages in the flash section size (bytes) page size (words) pages waddr paddr code (program memory) 2048 16 64 [4:1] [10:5] configuration 16 16 1 [4:1] ? signature (1) 32 16 2 [4:1] [5:5] calibration (1) 16 16 1 [4:1] ? table 19-4. configuration bytes configuration word address configuration word data high byte low byte 0x00 reserved configuration byte 0 0x01 ... 0x0f reserved reserved table 19-5. configuration byte 0 bit bit name description default value 7 ? reserved 1 (unprogrammed) 6 bodlevel2 (1) brown-out detector trigger level 1 (unprogrammed) 5 bodlevel1 (1) brown-out detector trigger level 1 (unprogrammed) 4 bodlevel0 (1) brown-out detector trigger level 1 (unprogrammed) 3 ? reserved 1 (unprogrammed) 2 ckout system clock output 1 (unprogrammed) 1 wdton watchdog timer always on 1 (unprogrammed) 0 rstdisbl external reset disable 1 (unprogrammed) 166 8235b?avr?04/11 attiny20 19.3.3.1 latching of configuration bits all configuration bits are latched either when the device is reset or when the device exits the external programming mode. changes to configuration bit values have no effect until the device leaves the external programming mode. 19.3.4 signature section the signature section is a dedicated memory area used for storing miscellaneous device infor- mation, such as the device signature. most of th is memory section is reserved for internal use, as shown in table 19-6 . attiny20 has a three-byte signature code, which can be used to identify the device. the three bytes reside in the signature section, as shown in table 19-6 . the signature data for attiny20 is given in table 19-7 . 19.3.5 calibration section attiny20 has one calibration byte. the calibration byte contains the calibration data for the inter- nal oscillator and resides in the calibration section, as shown in table 19-8 . during reset, the calibration byte is automatically written into the osccal register to ensure correct frequency of the calibrated internal oscillator. 19.3.5.1 latching of calibration value to ensure correct frequency of th e calibrated internal oscillator the calibration value is automati- cally written into the oscca l register during reset. table 19-6. signature bytes signature word address signature word data high byte low byte 0x00 device id 1 manufacturer id 0x01 reserved for internal use device id 2 0x02 ... 0x1f reserved for internal use reserved for internal use table 19-7. signature codes part signature bytes manufacturer id device id 1 device id 2 attiny20 0x1e 0x91 0x0f table 19-8. calibration byte calibration word address calibration word data high byte low byte 0x00 reserved internal oscillator calibration value 0x01 ... 0x0f reserved reserved 167 8235b?avr?04/11 attiny20 19.4 accessing the nvm nvm lock bits, and all flash memory sections are mapped to the data space as shown in figure 5-1 on page 16 . the nvm can be accessed for read and programming via the locations mapped in the data space. the nvm controller recognises a set of commands that can be used to instruct the controller what type of programming task to perform on the nvm. commands to the nvm controller are issued via the nvm command register. see ?nvmcmd ? non-volatile memory command register? on page 170 . after the selected command has been loaded, the operation is started by writing data to the nvm locations mapped to the data space. when the nvm controller is busy performing an oper ation it will signal this via the nvm busy flag in the nvm control and status register. see ?nvmcsr - non-volatile memory control and status register? on page 171 . the nvm command register is blocked for write access as long as the busy flag is active. this is to ensure that the current command is fully executed before a new command can start. programming any part of th e nvm will automatically inhibi t the following operations: ? all programming to any other part of the nvm ? all reading from any nvm location the attiny20 supports only external programming. internal programming operations to the nvm have been disabled, which means any internal a ttempt to write or erase nvm locations will fail. 19.4.1 addressing the flash the data space uses byte access ing but since the flash sections are accessed as words and organized in pages, the byte-address of the data space must be converted to the word-address of the flash section. this is illustrated in figure 19-1 . also, see table 19-3 on page 165 . figure 19-1. addressing the flash memory 00 pag e 01 02 s ectionend word 00 01 pageend fla s h s ection fla s h pag e 0/1 waddr paddr 1 waddrm s b paddrm s b 16 addre ss pointer ... ... ... ... ... ... page addre ss within a fla s h s ection word addre ss within a fla s h pag e low/high byte s elect waddrm s b+1 168 8235b?avr?04/11 attiny20 the most significant bits of the data space address select the nvm lock bits or the flash sec- tion mapped to the data memory. the word address within a page (waddr) is held by the bits [waddrmsb:1], and the page address (paddr) is held by the bi ts [paddrmsb:wad- drmsb+1]. together, paddr and waddr form the absolute address of a word in the flash section. the least significant bit of the flash section address is used to select the low or high byte of the word. 19.4.2 reading the flash the flash can be read from the data memory mapped locations one byte at a time. for read operations, the least significant bit (bit 0) is used to select the low or high byte in the word address. if this bit is zero, the low byte is re ad, and if it is one, the high byte is read. 19.4.3 programming the flash the flash can be written two words at a time. before writing a flash double word, the flash tar- get location must be er ased. writing to an un-erased fl ash word will corrupt its content. the flash is written two words at a time but the data space uses byte-addressing to access flash that has been mapped to data memory. it is therefore important to write the two words in the correct order to the flash, namely low bytes before high bytes. the low byte of the first word is first written to the temporary buffer, then the high byte. writing the low byte and then the high byte to the buffer latches the two words into the flash write buffer, starting the actual flash write operation. the flash erase operations can only performed for the entire flash sections. the flash programming sequence is as follows: 1. perform a flash section erase or perform a chip erase 2. write the flash section two words at a time 19.4.3.1 chip erase the chip erase command will erase the entire code section of the flash memory and the nvm lock bits. for security reasons, however, the nvm lock bits are not reset before the code sec- tion has been completely erased. the configuration, signature and calibration sections are not changed. before starting the chip erase, the nvmcmd register must be loaded with the chip_erase command. to start the erase operation a dummy byte must be written into the high byte of a word location that resides insi de the flash code sectio n. the nvmbsy bit rema ins set until eras- ing has been completed. while the flash is being erased neither flash buffer loading nor flash reading can be performed. the chip erase can be carried out as follows: 1. write the chip_erase command to the nvmcmd register 2. start the erase operation by writing a dummy byte to the high byte of any word location inside the code section 3. wait until the nvmbsy bit has been cleared 169 8235b?avr?04/11 attiny20 19.4.3.2 erasing the code section the algorithm for erasing all pages of the flash code section is as follows: 1. write the section_erase comm and to the nvmcmd register 2. start the erase operation by writing a dummy byte to the high byte of any word location inside the code section 3. wait until the nvmbsy bit has been cleared 19.4.3.3 writing a double code word the algorithm for writing two words to the code section is as follows: 1. write the dword_write command to the nvmcmd register 2. write the low byte of the low data word to the low byte of a target word location 3. write the high byte of the low data word to the high byte of the same target word location 4. send idle character as described in section ?supported characters? on page 154 5. write the low byte of the high data word to the low byte of the next target word location 6. write the high byte of the high data word to the high byte of the same target word loca- tion. this will start the flash write operation 7. wait until the nvmbsy bit has been cleared 19.4.3.4 erasing the configuration section the algorithm for erasing the configuration section is as follows: 1. write the section_erase comm and to the nvmcmd register 2. start the erase operation by writing a dummy byte to the high byte of any word location inside the configuration section 3. wait until the nvmbsy bit has been cleared 19.4.3.5 writing a configuration word the algorithm for writing a conf iguration word is as follows. 1. write the dword_write command to the nvmcmd register 2. write the low byte of the data word to the low byte of the configuration word location 3. write the high byte of the data word to the high byte of the same configuration word location 4. send idle character as described in section ?supported characters? on page 154 5. write a dummy byte to the low byte of the next configuration word location 6. write a dummy byte to the high byte of th e same configuration word location. this will start the flash write operation 7. wait until the nvmbsy bit has been cleared 19.4.4 reading nvm lock bits the non-volatile memory lock byte can be read from the mapped location in data memory. 170 8235b?avr?04/11 attiny20 19.4.5 writing nvm lock bits the algorithm for writing the lock bits is as follows. 1. write the dword_write command to the nvmcmd register. 2. write the lock bits value to the non-volatile memory lock byte loca tion. this is the low byte of the non-volatile memory lock word. 3. start the nvm lock bit write operation by writing a dummy byte to the high byte of the nvm lock word location. 4. wait until the nvmbsy bit has been cleared. 19.5 self programming the attiny20 doesn't support internal programming. 19.6 external programming the method for programming the non-volatile memories by means of an external programmer is referred to as external programming. external programming can be done both in-system or in mass production. the non-volatile memories can be externally programmed via the tiny programming interface (tpi). for details on the tpi, see ?programming interface? on page 152 . using the tpi, the external programmer can access the nvm control and status registers mapped to i/o space and the nvm memory mapped to data memory space. 19.6.1 entering external programming mode the tpi must be enabled before external programming mode can be entered. the following pro- cedure describes, how to enter the external programming mode after the tpi has been enabled: 1. make a request for enabling nvm programming by sending the nvm memory access key with the skey instruction. 2. poll the status of the nvmen bit in tpisr until it has been set. refer to the tiny programming interface description on page 152 for more detailed information of enabling the tpi and programming the nvm. 19.6.2 exiting external programming mode clear the nvm enable bit to disable nvm programming, then release the reset pin. see nvmen bit in ?tpisr ? tiny programming interface status register? on page 162 . 19.7 register description 19.7.1 nvmcmd ? non-volatile memory command register ? bits 7:6 ? res: reserved bits these bits are reserved and will always read as zero. bit 76543210 0x33 ? ? nvmcmd[5:0] nvmcmd read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 171 8235b?avr?04/11 attiny20 ? bits 5:0 ? nvmcmd[5:0]: non-volatile memory command these bits define the programming commands for the flash, as shown in table 19-9 . 19.7.2 nvmcsr - non-volatile memory control and status register ? bit 7 ? nvmbsy: non-volatile memory busy this bit indicates the nvm memory (flash memory and lock bits) is busy, being programmed. this bit is set when a program operation is star ted, and it remains set until the operation has been completed. ? bits 6:0 ? res: reserved bits these bits are reserved and will always read as zero. table 19-9. nvm programming commands operation type nvmcmd mnemonic description binary hex general 0b000000 0x00 no_operation no operation 0b010000 0x10 chip_erase chip erase section 0b010100 0x14 section_erase section erase double word 0b011101 0x1d dword_write write double word bit 7 6543210 0x32 nvmbsy???????nvmcsr read/writer/wrrrrrrr initial value0 0000000 172 8235b?avr?04/11 attiny20 20. electrical characteristics 20.1 absolute maximum ratings * 20.2 dc characteristics operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins ................................ 200.0 ma table 20-1. dc characteristics. t a = -40 c to +85 c symbol parameter condition min typ (1) max units v il input low voltage v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 0.2v cc (3) 0.3v cc (3) v v ih input high-voltage except reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc +0.5 v input high-voltage reset pin v cc = 1.8v to 5.5v 0.9v cc (2) v cc +0.5 v v ol output low voltage (4) except reset pin (6) i ol = 10 ma, v cc = 5v i ol = 5 ma, v cc = 3v i ol = 2ma, v cc = 1.8v 0.6 0.5 0.4 v v oh output high-voltage (5) except reset pin (6) i oh = -10 ma, v cc = 5v i oh = -5 ma, v cc = 3v i oh = -2 ma, v cc = 1.8v 4.3 2.5 1.4 v i lil input leakage current i/o pin vcc = 5.5v, pin low (absolute value) <0.05 1 a i lih input leakage current i/o pin vcc = 5.5v, pin high (absolute value) <0.05 1 a r rst reset pull-up resistor vcc = 5.5v, input low 30 60 k r pu i/o pin pull-up resistor vcc = 5.5v, input low 20 50 k i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na 173 8235b?avr?04/11 attiny20 notes: 1. typical values at 25 c. 2. ?min? means the lowest value where t he pin is guaranteed to be read as high. 3. ?max? means the highest value where the pin is guaranteed to be read as low. 4. although each i/o port can sink more than the test conditions (10 ma at v cc = 5v, 5 ma at v cc = 3v) under steady state conditions (non-transient), the sum of all i ol (for all ports) should not exceed 100 ma. if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guarante ed to sink current greater th an the listed test condition. 5. although each i/o port can source more than the test conditions (10 ma at v cc = 5v, 5 ma at v cc = 3v) under steady state conditions (non-transient), the sum of all i oh (for all ports) should not exceed 100 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 6. the reset pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared to regular i/o pins. see figure 21-30 on page 195 , and figure 21-33 on page 196 . 7. values are with external clock using methods described in ?minimizing power consumption? on page 27 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 8. bod disabled. i cc power supply current (7) active 1 mhz, v cc = 2v 0.2 0.6 ma active 4 mhz, v cc = 3v 1.1 2 ma active 8 mhz, v cc = 5v 3.2 5 ma idle 1 mhz, v cc = 2v 0.03 0.2 ma idle 4 mhz, v cc = 3v 0.2 0.5 ma idle 8 mhz, v cc = 5v 0.8 1.5 ma power-down mode (8) wdt enabled, v cc = 3v 4.5 10 a wdt disabled, v cc = 3v 0.15 2 a table 20-1. dc characteristics. t a = -40 c to +85 c (continued) symbol parameter condition min typ (1) max units 174 8235b?avr?04/11 attiny20 20.3 speed the maximum operating frequency of the device is dependent on supply voltage, v cc . the rela- tionship between supply voltage and maximum operating frequency is piecewise linear, as shown in figure 20-1 , the maximum frequency vs. v cc curve is linear between 1.8v < v cc < 4.5v. figure 20-1. maximum operating frequency vs. supply voltage 20.4 clock characteristics 20.4.1 accuracy of calibrated internal oscillator it is possible to manua lly calibrate the internal oscillator to be more accu rate than def ault factory calibration. note that the osc illator frequency depend s on temperat ure and voltage. voltage and temperature characteristics can be found in figure 21-53 on page 206 and figure 21-54 on page 207 . notes: 1. accuracy of oscillator frequency at calibra tion point (fixed temperature and fixed voltage). 4 mhz 1. 8 v 5.5v 4.5v 12 mhz 2.7v 8 mhz table 20-2. calibration accuracy of internal rc oscillator calibration method target frequency v cc temperature accuracy at given voltage & temperature (1) factory calibration 8.0 mhz 3v 25 c10% user calibration fixed frequency within: 7.3 ? 8.1 mhz fixed voltage within: 1.8v ? 5.5v fixed temp. within: -40 c to +85 c 1% 175 8235b?avr?04/11 attiny20 20.4.2 external clock drive figure 20-2. external clock drive waveform 20.5 system and reset characteristics note: 1. values are guidelines, only v il1 v ih1 table 20-3. external clock drive characteristics symbol parameter v cc = 1.8 - 5.5v v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. min. max. 1/t clcl clock frequency 0 4 0 8 0 12 mhz t clcl clock period 250 125 83 ns t chcx high time 100 40 20 ns t clcx low time 100 40 20 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 2 2 2 % table 20-4. reset and internal voltage characteristics symbol parameter condition min (1) typ (1) max (1) units v rst reset pin threshold voltage 0.2 v cc 0.9v cc v v bg internal bandgap voltage v cc = 2.7v t a =25c 1.0 1.1 1.2 v t rst minimum pulse width on reset pin v cc = 1.8v v cc = 3v v cc = 5v 2000 700 400 ns t tout time-out after reset bod disabled 64 128 ms bod enabled 128 256 176 8235b?avr?04/11 attiny20 20.5.1 power-on reset note: 1. values are guidelines, only 2. threshold where device is released from reset when voltage is rising 3. the power-on reset will not work unless the supply voltage has been below v pot (falling) 20.5.2 brown-out detection note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 20.6 analog comparat or characteristics table 20-5. characteristics of enhanced power-on reset. t a = -40 to +85 c symbol parameter min (1) typ (1) max (1) units v por release threshold of power-on reset (2) 1.1 1.4 1.6 v v poa activation threshold of power-on reset (3) 0.6 1.3 1.6 v sr on power-on slope rate 0.01 v/ms table 20-6. v bot vs. bodlevel fuse coding bodlevel[2:0] fuses min (1) typ (1) max (1) units 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.1 4.3 4.5 0xx reserved table 20-7. analog comparator characteristics, t a = -40 c to +85 c symbol parameter condi tion min typ max units v aio input offset voltage v cc = 5v, vin = v cc / 2 < 10 40 mv i lac input leakage current v cc = 5v, vin = v cc / 2 -50 50 na t apd analog propagation delay (from saturation to slight overdrive) v cc = 2.7v 750 ns v cc = 4.0v 500 analog propagation delay (large step change) v cc = 2.7v 100 v cc = 4.0v 75 t dpd digital propagation delay v cc = 1.8v - 5.5 1 2 clk 177 8235b?avr?04/11 attiny20 20.7 adc characteristics 20.8 serial programming characteristics figure 20-3. serial programming timing table 20-8. adc characteristics. t = -40 c to +85 c. v cc = 1.8 ? 5.5v symbol parameter condition min typ max units resolution 10 bits absolute accuracy (including inl, dnl, and quantization, gain and offset errors) v ref = v cc = 4v, adc clock = 200 khz 2lsb v ref = v cc = 4v, adc clock = 1 mhz 3lsb v ref = v cc = 4v, adc clock = 200 khz noise reduction mode 1.5 lsb v ref = v cc = 4v, adc clock = 1 mhz noise reduction mode 2.5 lsb integral non-linearity (inl) (accuracy after offset and gain calibration) v ref = v cc = 4v, adc clock = 200 khz 1lsb differential non-linearity (dnl) v ref = v cc = 4v, adc clock = 200 khz 0.5 lsb gain error v ref = v cc = 4v, adc clock = 200 khz 2.5 lsb offset error v ref = v cc = 4v, adc clock = 200 khz 1.5 lsb conversion time free running conversion 13 260 s clock frequency 50 1000 khz v in input voltage gnd v ref v input bandwidth 38.5 khz r ain analog input resistance 100 m adc conversion output 0 1023 lsb t chix tpid ata t ivch t chcl t clc h t clcl tpic lk t clo v transmit mode rec eive mode 178 8235b?avr?04/11 attiny20 table 20-9. serial programming characteristics. symbol parameter min typ max units v cc programming voltage 4.75 5 5.5 v f clcl clock frequency 2 mhz t clcl clock period 500 ns t clch clock low pulse width 200 ns t chch clock high pulse width 200 ns t ivch data input to clock high setup time 50 ns t chix data input hold time after clock high 100 ns t clov data output valid after clock low time 200 ns 179 8235b?avr?04/11 attiny20 21. typical characteristics the data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. thus, the data should be treated as indica- tions of how the part will behave. the following charts show typical behavior. t hese figures are not tested during manufacturing. during characterisation devices are operated at fr equencies higher than test limits but they are not guaranteed to function properly at frequencies higher than the ordering code indicates. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. current consumption is a function of several factors such as oper- ating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. a sine wave generator with rail-to-rail output is used as clock source but current consumption in power-down mode is independent of clock selection. the difference between current consump- tion in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. the current drawn from pins with a capacitive lo ad may be estimated (for one pin) as follows: where v cc = operating voltage, c l = load capacitance and f sw = average switching frequency of pin. 21.1 supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules is controlled by the powe r reduction register. see ?power reduction register? on page 27 for details. i cp v cc c l f sw table 21-1. additional current consumption for different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prtim0 4 a 25 a 110 a prtim1 5 a 35 a 150 a pradc 190 a 260 a 470 a prspi 3 a 15 a 75 a prtwi 5 a 35 a 160 a 180 8235b?avr?04/11 attiny20 table 21-2 below can be used for calculating typical current consumption for other supply volt- ages and frequencies than those mentioned in the table 21-1 above. 21.2 current consumption in active mode figure 21-1. active supply current vs. low frequency (0.1 - 1.0 mhz) table 21-2. additional current consumption (percentage) in active and idle mode prr bit current consumptio n additional to active mode with external clock (see figure 21-1 and figure 21-2 ) current consumption additional to idle mode with external clock (see figure 21-6 and figure 21-7 ) prtim0 2 % 15 % prtim1 3 % 20 % pradc see figure 21-14 on page 187 see figure 21-14 on page 187 prtspi 2 % 10 % prttwi 4 % 20 % active supply current vs. low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency [mhz] icc [ma] 181 8235b?avr?04/11 attiny20 figure 21-2. active supply current vs . frequency (1 - 12 mhz) figure 21-3. active supply current vs. v cc (internal oscillator, 8 mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v active supply current vs. frequency 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 6 2 1 0 1 8 6 4 2 0 frequency [mhz] icc [ma] active supply current vs. v cc internal rc oscillator, 8 mhz 0 0,5 1 1,5 2 2,5 3 3,5 4 1,5 2 2,5 3 3,5 4 4,5 5 vcc [v] icc [ma] 85 c 25 c -40 c 182 8235b?avr?04/11 attiny20 figure 21-4. active supply current vs. v cc (internal oscillator, 1 mhz) figure 21-5. active supply current vs. v cc (internal oscillator, 128 khz) 85 c 25 c -40 c active supply current vs. v cc internal rc oscillator, 1 mhz 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,522,533,544,555,5 vcc [v] icc [ma] active supply current vs. v cc internal rc oscillator, 128 khz 0 0,02 0,04 0,06 0,08 0,1 0,12 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ma] 85 c 25 c -40 c 183 8235b?avr?04/11 attiny20 21.3 current consumption in idle mode figure 21-6. idle supply current vs. low frequency (0.1 - 1.0 mhz) figure 21-7. idle supply current vs. frequency (1 - 12 mhz) idle supply current vs. low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0,02 0,04 0,06 0,08 0,1 0,12 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency [mhz] icc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v idle supply current vs. frequency 0 0,2 0,4 0,6 0,8 1 1,2 1,4 2 1 0 1 8 6 4 2 0 frequency [mhz] icc [ma] 184 8235b?avr?04/11 attiny20 figure 21-8. idle supply current vs. v cc (internal osc illator, 8 mhz) figure 21-9. idle supply current vs. v cc (internal osc illator, 1 mhz) idle supply current vs. v cc internal rc oscillator, 8 mhz 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ma] 85 c 25 c -40 c idle supply current vs. v cc internal rc oscillator, 1 mhz 0 0,05 0,1 0,15 0,2 0,25 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ma] 85 c 25 c -40 c 85 c 25 c -40 c 185 8235b?avr?04/11 attiny20 figure 21-10. idle supply current vs. v cc (internal osc illator, 128 khz) 21.4 current consumption in power-down mode figure 21-11. power-down supply current vs. v cc (watchdog timer disabled) idle supply current vs. v cc internal rc oscillator, 128 khz 0 0,005 0,01 0,015 0,02 0,025 0,03 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ma] 85 c 25 c -40 c 85 c 25 c -40 c power-down supply current vs. v cc watchdog timer disabled 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0,45 1,522,533,544,555,5 vcc [v] icc [ua] 85 c 25 c -40 c 186 8235b?avr?04/11 attiny20 figure 21-12. power-down supply current vs. v cc (watchdog timer enabled) 21.5 current consumption in reset figure 21-13. reset supply current vs. v cc (excluding current through the reset pull-up and no clock) 85 c 25 c -40 c power-down supply current vs. v cc watchdog timer enabled 0 1 2 3 4 5 6 7 8 9 10 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ua] reset current vs. v cc excluding current through the reset pullup and no clock 0 0,2 0,4 0,6 0,8 1 1,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ma] 25 c 85 c -40 c 187 8235b?avr?04/11 attiny20 21.6 current consumption of peripheral units figure 21-14. adc current vs. v cc (at clk adc = 250khz) figure 21-15. analog comparator current vs. v cc adc current vs. v cc 0 50 100 150 200 250 300 350 400 450 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] i cc [ua] analog comparator current vs. v cc 0 10 20 30 40 50 60 70 80 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] i cc [ua] 188 8235b?avr?04/11 attiny20 figure 21-16. watchdog timer current vs. v cc figure 21-17. brownout detector current vs. v cc watchdog timer current vs. v cc 0 1 2 3 4 5 6 7 8 9 10 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] icc [ua] 85 c 25 c -40 c brownout detector current vs. v cc 0 5 10 15 20 25 30 35 40 45 1,522,533,544,555,5 vcc [v] icc [ua] 85 c 25 c -40 c 189 8235b?avr?04/11 attiny20 21.7 pull-up resistors figure 21-18. i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 21-19. i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) i/o pin pull-up resistor current vs. input voltage 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vop [v] iop [ua] 85 c 25 c -40 c 85 c 25 c -40 c i/o pin pull-up resistor current vs. input voltage 0 10 20 30 40 50 60 70 80 3 5 , 2 2 5 , 1 1 5 , 0 0 vop [v] iop [ua] 190 8235b?avr?04/11 attiny20 figure 21-20. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 21-21. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 1.8v) 85 c 25 c -40 c i/o pin pull-up resistor current vs. input voltage 0 20 40 60 80 100 120 140 160 6 5 4 3 2 1 0 vop [v] iop [ua] 25 c 85 c -40 c reset pull-up resistor current vs. reset pin voltage 0 5 10 15 20 25 30 35 40 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vreset [v] ireset [ua] 191 8235b?avr?04/11 attiny20 figure 21-22. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 2.7v) figure 21-23. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 5v) 25 c 85 c -40 c reset pull-up resistor current vs. reset pin voltage 0 10 20 30 40 50 60 3 5 , 2 2 5 , 1 1 5 , 0 0 vreset [v] ireset [ua] 25 c 85 c -40 c reset pull-up resistor current vs. reset pin voltage 0 20 40 60 80 100 120 6 5 4 3 2 1 0 vreset [v] ireset [ua] 192 8235b?avr?04/11 attiny20 21.8 output driver strength figure 21-24. v ol : output voltage vs. sink current (i/o pin, v cc = 1.8v) figure 21-25. v ol : output voltage vs. sink current (i/o pin, v cc = 3v) 85 c 25 c 85 c 25 c -40 c i/o pin output voltage vs. sink current v cc = 1.8v 0 0,2 0,4 0,6 0,8 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 i ol [ma] v ol [v] 85 c 85 c 25 c -40 c i/o pin output voltage vs. sink current v cc = 3v 0 0,2 0,4 0,6 0,8 012345678910 i ol [ma] v ol [v] 193 8235b?avr?04/11 attiny20 figure 21-26. v ol : output voltage vs. sink current (i/o pin, v cc = 5v) figure 21-27. v oh : output voltage vs. source current (i/o pin, v cc = 1.8v) 85 c 85 c 25 c -40 c i/o pin output voltage vs. sink current v cc = 5v 0 0,2 0,4 0,6 0,8 1 0 2 4 6 8 101214161820 i ol [ma] v ol [v] 85 c 25 c -40 c i/o pin output voltage vs. source current v cc = 1.8v 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 3 5 , 2 2 5 , 1 1 5 , 0 0 i oh [ma] v oh [v] 194 8235b?avr?04/11 attiny20 figure 21-28. v oh : output voltage vs. source current (i/o pin, v cc = 3v) figure 21-29. v oh : output voltage vs. source current (i/o pin, v cc = 5v) -40 c 85 c 25 c i/o pin output voltage vs. source current v cc = 3v 1,6 1,8 2 2,2 2,4 2,6 2,8 3 3,2 012345678910 i oh [ma] v oh [v] -40 c 85 c 25 c i/o pin output voltage vs. source current v cc = 5v 3,8 4 4,2 4,4 4,6 4,8 5 5,2 0 2 4 6 8 101214161820 i oh [ma] v oh [v] 195 8235b?avr?04/11 attiny20 figure 21-30. v ol : output voltage vs. sink current (reset pin as i/o, v cc = 1.8v) figure 21-31. v ol : output voltage vs. sink current (reset pin as i/o, v cc = 3v) 25 c 85 c -40 c reset as i/o output voltage vs. sink current vcc = 1.8v 0 0,2 0,4 0,6 0,8 1 6 , 0 5 , 0 4 , 0 3 , 0 2 , 0 1 , 0 0 iol [ma] vol [v] 25 c 85 c -40 c reset as i/o output voltage vs. sink current vcc = 3v 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 3 5 , 2 2 5 , 1 1 5 , 0 0 iol [ma] vol [v] 196 8235b?avr?04/11 attiny20 figure 21-32. v ol : output voltage vs. sink current (reset pin as i/o, v cc = 5v) figure 21-33. v oh : output voltage vs. source current (reset pin as i/o, v cc = 1.8v 25 c 85 c -40 c reset as i/o output voltage vs. sink current vcc = 5v 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 iol [ma] vol [v] 25 c 85 c -40 c reset as i/o output voltage vs. source current vcc = 1.8v 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 ioh [ma] voh [v] 197 8235b?avr?04/11 attiny20 figure 21-34. v oh : output voltage vs. source current (reset pin as i/o, v cc = 3v figure 21-35. v oh : output voltage vs. source current (reset pin as i/o, v cc = 5v 25 c 85 c -40 c reset as i/o output voltage vs. source current vcc = 3v 0 0,5 1 1,5 2 2,5 3 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 ioh [ma] voh [v] 25 c 85 c -40 c reset as i/o output voltage vs. source current vcc = 5v 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 ioh [ma] voh [v] 198 8235b?avr?04/11 attiny20 21.9 input thresholds and hysteresis figure 21-36. v ih : input threshold voltage vs. v cc (i/o pin, read as ?1?) figure 21-37. v il : input threshold voltage vs. v cc (i/o pin, read as ?0?) i/o pin input threshold voltage vs. v cc vih, io pin read as '1' 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] threshold [v] 85 c 25 c -40 c 85 c 25 c -40 c 25 c 85 c -40 c reset input threshold voltage vs. v cc vil, chip reset 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] threshold [v] 199 8235b?avr?04/11 attiny20 figure 21-38. v ih -v il : input hysteresis vs. v cc (i/o pin) figure 21-39. v ih : input threshold voltage vs. v cc (reset pin as i/o, read as ?1?) 25 c 85 c -40 c i/o pin input hysteresis 0 0,1 0,2 0,3 0,4 0,5 0,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] hysteresis [v] reset pin as i/o threshold voltage vs. v cc vih, reset read as '1' 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] threshold [v] 25 c 85 c -40 c 200 8235b?avr?04/11 attiny20 figure 21-40. v il : input threshold voltage vs. v cc (reset pin as i/o, read as ?0?) figure 21-41. v ih -v il : input hysteresis vs. v cc (reset pin as i/o) 25 c 85 c -40 c reset pin as i/o threshold voltage vs. v cc vil, reset read as '0' 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] threshold [v] 25 c 85 c -40 c reset as i/o input hysteresis 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] hysteresis [v] 201 8235b?avr?04/11 attiny20 21.10 bod, bandgap and reset figure 21-42. bod threshold vs temperat ure (bodlevel is 4.3v) figure 21-43. bod threshold vs temperat ure (bodlevel is 2.7v) v cc rising v cc falling bod thresholds vs. temperature bod level 4.3 v 4,18 4,2 4,22 4,24 4,26 4,28 4,3 4,32 4,34 -40-20 0 20406080100 temperature [c] threshold [v] v cc rising v cc falling bod thresholds vs. temperature bod level 2.7 v 2,64 2,65 2,66 2,67 2,68 2,69 2,7 2,71 2,72 2,73 2,74 2,75 -40 -20 0 20 40 60 80 100 temperature [c] threshold [v] 202 8235b?avr?04/11 attiny20 figure 21-44. bod threshold vs temperat ure (bodlevel is 1.8v) figure 21-45. bandgap voltage vs. supply voltage bod thresholds vs. temperature bod level 1.8 v v cc rising 1,77 1,775 1,78 1,785 1,79 1,795 1,8 1,805 1,81 1,815 -40 -20 0 20 40 60 80 100 temperature [c] threshold [v] v cc falling 25 c 85 c -40 c bandgap voltage vs. vcc 1 1,01 1,02 1,03 1,04 1,05 1,06 1,07 1,08 1,09 1,1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] reference [v] 203 8235b?avr?04/11 attiny20 figure 21-46. v ih : input threshold voltage vs. v cc (reset pin, read as ?1?) figure 21-47. v il : input threshold voltage vs. v cc (reset pin, read as ?0?) reset input threshold voltage vs. v cc vih, reset released 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] threshold [v] 25 c 85 c -40 c 25 c 85 c -40 c reset input threshold voltage vs. v cc vil, chip reset 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] threshold [v] 204 8235b?avr?04/11 attiny20 figure 21-48. v ih -v il : input hysteresis vs. v cc (reset pin ) figure 21-49. minimum reset pulse width vs. v cc 25 c 85 c -40 c reset input hysteresis 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] hysteresis [v] minimum reset pulse width vs. v cc 85 25 -40 0 500 1000 1500 2000 2500 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc [v] pulsewidth [ns] 205 8235b?avr?04/11 attiny20 21.11 analog comparator offset figure 21-50. analog comparator offset 21.12 internal oscillator speed figure 21-51. watchdog oscillato r frequency vs. v cc 85 c 25 c -40 c analog comparator offset v cc = 5v -0,016 -0,014 -0,012 -0,01 -0,008 -0,006 -0,004 -0,002 0 0,002 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 v in (v) offset (v) -40 c 85 c 25 c watchdog oscillator frequency vs. operating voltage 0,098 0,099 0,1 0,101 0,102 0,103 0,104 0,105 0,106 0,107 0,108 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] frc [mhz] 206 8235b?avr?04/11 attiny20 figure 21-52. watchdog oscillator freq uency vs. temperature figure 21-53. calibrated oscillator frequency vs. v cc watchdog oscillator frequency vs. temperature 5.5 v 4.0 v 3.5 v 2.8 v 1.8 v 0,106 0,108 0,11 0,112 0,114 0,116 0,118 -40 -20 0 20 40 60 80 100 temperature [c] frc [mhz] 85 c 25 c -40 c calibrated 8mhz rc oscillator frequency vs. operating voltage 7,4 7,6 7,8 8 8,2 8,4 1,5 2 2,5 3 3,5 4 4,5 5 5,5 vcc [v] frc [mhz] 207 8235b?avr?04/11 attiny20 figure 21-54. calibrated oscillator freq uency vs. temperature figure 21-55. calibrated oscillator freq uency vs. osccal value calibrated 8mhz rc oscillator frequency vs. temperature 5.0 v 3.0 v 1.8 v 7,6 7,7 7,8 7,9 8 8,1 8,2 8,3 -40 -20 0 20 40 60 80 100 temperature [c] frc [mhz] calibrated 8.0mhz rc oscillator frequency vs. osccal value 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 osccal [x1] frc [mhz] 85 c 25 c -40 c 208 8235b?avr?04/11 attiny20 22. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f sreg i t h s v n z c page 14 0x3e sph stack pointer high byte page 13 0x3d spl stack pointer low byte page 13 0x3c ccp cpu change protection byte page 13 0x3b rstflr ? ? ? ? wdrf borf extrf porf page 37 0x3a mcucr icsc01 icsc00 ? bods sm2 sm1 sm0 se pages 28 , 41 0x39 osccal oscillator ca libration byte page 23 0x38 reserved ? ? ? ? ? ? ? ? 0x37 clkmsr ? ? ? ? ? ? clkms1 clkms0 page 22 0x36 clkpsr ? ? ? ? clkps3 clkps2 clkps1 clkps0 page 22 0x35 prr ? ? ? prtwi prspi prtim1 prtim0 pradc page 29 0x34 qtcsr qtouch control and status register page 6 0x33 nvmcmd ? ? nvm command page 170 0x32 nvmcsr nvmbsy ? ? ? ? ? ? ? page 171 0x31 wdtcsr wdif wdie wdp3 ? wde wdp2 wdp1 wdp0 page 35 0x30 spcr spie spe dord mstr cpol cpha spr1 spr0 page 135 0x2f spsr spif wcol ? ? ? ? ssps spi2x page 137 0x2e spdr spi data register page 137 0x2d twscra twshe ? twdie twasie twen twsie twpme twsme page 146 0x2c twscrb ? ? ? ? ? twaa twcmd[1.0] page 147 0x2b twssra twdif twasif twch twra twc twbe twdir twas page 148 0x2a twsa twi slave address register page 150 0x29 twsam twi slave address mask register page 151 0x28 twsd twi slave data register page 150 0x27 gtccr tsm ? ? ? ? ? ? psr page 107 0x26 timsk ice1 ? ocie1b ocie1a toie1 ocie0b ocie0a toie0 pages 76 , 103 0x25 tifr icf1 ? ocf1b ocf1a tov1 ocf0b ocf0a tov0 pages 76 , 104 0x24 tccr1a com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 page 99 0x23 tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 101 0x22 tccr1c foc1a foc1b ? ? ? ? ? ? page 102 0x21 tcnt1h timer/counter1 ? counter register high byte page 102 0x20 tcnt1l timer/counter1 ? counter register low byte page 102 0x1f ocr1ah timer/counter1 ? compare register a high byte page 103 0x1e ocr1al timer/counter1 ? compare register a low byte page 103 0x1d ocr1bh timer/counter1 ? compare register b high byte page 103 0x1c ocr1bl timer/counter1 ? compare register b low byte page 103 0x1b icr1h timer/counter1 - input capture register high byte page 103 0x1a icr1l timer/counter1 - input capture register low byte page 103 0x19 tccr0a com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 page 71 0x18 tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 74 0x17 tcnt0 timer/counter0 ? counter register page 75 0x16 ocr0a timer/counter0 ? compare register a page 75 0x15 ocr0b timer/counter0 ? compare register b page 76 0x14 acsra acd acbg aco aci acie acic acis1 acis0 page 109 0x13 acsrb hsel hlev aclp ? acce acme acirs1 acirs0 page 110 0x12 adcsra aden adsc adate adif adie adps2 adps1 adps0 page 126 0x11 adcsrb vden vdpd ? ? adlar adts2 adts1 adts0 page 127 0x10 admux ? refs refen adc0en mux3 mux2 mux1 mux0 page 124 0x0f adch adc conversion result ? high byte page 125 0x0e adcl adc conversion result ? low byte page 125 0x0d didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d page 128 0x0c gimsk ? ? pcie1 pcie0 ? ? ? int0 page 41 0x0b gifr ? ? pcif1 pcif0 ? ? ? intf0 page 42 0x0a pcmsk1 ? ? ? ? pcint11 pcint10 pcint9 pcint8 page 43 0x09 pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 page 43 0x08 portcr ? ? ? ? ? ? bbmb bbma page 58 0x07 pueb ? ? ? ? pueb3 pueb2 pueb1 pueb0 page 58 0x06 portb ? ? ? ? portb3 portb2 portb1 portb0 page 59 0x05 ddrb ? ? ? ? ddrb3 ddrb2 ddrb1 ddrb0 page 59 0x04 pinb ? ? ? ? pinb3 pinb2 pinb1 pinb0 page 59 0x03 puea puea7 puea6 puea5 puea4 puea3 puea2 puea1 puea0 page 58 0x02 porta porta7 porta6 porta5 porta 4 porta3 porta2 porta1 porta0 page 58 0x01 ddra ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 page 58 0x00 pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 58 209 8235b?avr?04/11 attiny20 note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specified bit, and can theref ore be used on registers contai ning such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 210 8235b?avr?04/11 attiny20 23. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd rd + rr + c z,c,n,v,s,h 1 sub rd, rr subtract without carry rd rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd rd - k - c z,c,n,v,s,h 1 and rd, rr logical and rd rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd rd ? k z,n,v,s 1 or rd, rr logical or rd rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd rd v k z,n,v,s 1 eor rd, rr exclusive or rd rd rr z,n,v,s 1 com rd one?s complement rd $ff ? rd z,c,n,v,s 1 neg rd two?s complement rd $00 ? rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd rd + 1 z,n,v,s 1 dec rd decrement rd rd ? 1 z,n,v,s 1 tst rd test for zero or minus rd rd ? rd z,n,v,s 1 clr rd clear register rd rd rd z,n,v,s 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) z, pc(21:16) 0none2 rcall k relative subroutine call pc pc + k + 1 none 3/4 icall indirect call to (z) pc(15:0) z, pc(21:16) 0none3/4 ret subroutine return pc stack none 4/5 reti interrupt return pc stack i 4/5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, c,n,v,s,h 1 cpc rd,rr compare with carry rd ? rr ? c z, c,n,v,s,h 1 cpi rd,k compare with immediate rd ? k z, c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b)=0) pc pc + 2 or 3 none 1/2/3 sbis a, b skip if bit in i/o register is set if (i/o(a,b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 211 8235b?avr?04/11 attiny20 bclr s flag clear sreg(s) 0 sreg(s) 1 sbi a, b set bit in i/o register i/o(a, b) 1none1 cbi a, b clear bit in i/o register i/o(a, b) 0none1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set two?s complement overflow. v 1v1 clv clear two?s complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr copy register rd rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 1/2 ld rd, x+ load indirect and post-increment rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-decrement x x - 1, rd (x) none 2/3 ld rd, y load indirect rd (y) none 1/2 ld rd, y+ load indirect and post-increment rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-decrement y y - 1, rd (y) none 2/3 ld rd, z load indirect rd (z) none 1/2 ld rd, z+ load indirect and post-increment rd (z), z z+1 none 2 ld rd, -z load indirect and pre-decrement z z - 1, rd (z) none 2/3 lds rd, k store direct from sram rd ( k) none 1 st x, rr store indirect (x) rr none 1 st x+, rr store indirect and post-increment (x) rr, x x + 1 none 1 st - x, rr store indirect and pre-decrement x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 1 st y+, rr store indirect and post-increment (y) rr, y y + 1 none 1 st - y, rr store indirect and pre-decrement y y - 1, (y) rr none 2 st z, rr store indirect (z) rr none 1 st z+, rr store indirect and post-increment. (z) rr, z z + 1 none 1 st -z, rr store indirect and pre-decrement z z - 1, (z) rr none 2 sts k, rr store direct to sram (k) rr none 1 in rd, a in from i/o location rd i/o (a) none 1 out a, rr out to i/o location i/o (a) rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks 212 8235b?avr?04/11 attiny20 24. ordering information notes: 1. code indicators: ? h: nipdau lead finish ? u: matte tin ? r: tape & reel 2. all packages are pb-free, halide-free and fully green and they comply with the european directive for restriction of hazard- ous substances (rohs). 3. topside marking for attiny20: ? 1st line: t20 ? 2nd & 3rd line: manufacturing data 4. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 24.1 attiny20 speed (mhz) power supply ordering code (1) package (2) operational range 12 1.8 - 5.5v attiny20-ssu attiny20-ssur attiny20-xu attiny20-xur attiny20-ccu attiny20-ccur attiny20-mmh (3) attiny20-mmhr (3) 14s1 14s1 14x 14x 15cc1 15cc1 20m2 20m2 industrial (-40 c to +85 c) (4) package type 14s1 14-lead, 0.150" wide body, plastic gull wing small outline package (soic) 14x 14-lead, 4.4 mm body, thin shrink small outline package (tssop) 15cc1 15-ball (4 x 4 array), 0.65 mm pitch, 3.0 x 3.0 x 0.6 mm , ultra thin, fine-pitch ball grid array package (ufbga) 20m2 20-pad, 3 x 3 x 0.85 mm body, very thin quad flat no lead package (vqfn) 213 8235b?avr?04/11 attiny20 25. packaging information 25.1 14s1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 14s1 , 14-lead, 0.150" w ide body, plastic g u ll w ing small o u tline package (soic) 2/5/02 14s1 a a1 e l side v iew top v iew end v iew h e b n 1 e a d common dimensions (unit of meas u re = mm/inches) symbol min nom max note n otes: 1. this drawing is for general information only; refer to jedec drawing ms-012, v ariation ab for additional information. 2. dimension d does not incl u de mold flash, protr u sions or gate bu rrs. mold flash, protr u sion and gate bu rrs shall not exceed 0.15 mm (0.006") per side. 3. dimension e does not incl u de inter-lead flash or protr u sion. inter-lead flash and protr u sions shall not exceed 0.25 mm (0.010") per side. 4. l is the length of the terminal for soldering to a s ub strate. 5. the lead width b, as meas u red 0.36 mm (0.014") or greater a b o v e the seating plane, shall not exceed a maxim u m v al u e of 0.61 mm (0.024") per side. a 1.35/0.0532 ? 1.75/0.06 88 a1 0.1/.0040 ? 0.25/0.009 8 b 0.33/0.0130 ? 0.5/0.0200 5 d 8 .55/0.3367 ? 8 .74/0.3444 2 e3. 8 /0.1497 ? 3.99/0.1574 3 h5. 8 /0.22 8 4 ? 6.19/0.2440 l 0.41/0.0160 ? 1.27/0.0500 4 e 1.27/0.050 bsc 214 8235b?avr?04/11 attiny20 25.2 14x 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. y . . 14x (formerly "14t") , 14-lead (4.4 mm body) thin shrink small outline package (tssop) b 14x 05/16/01 5.10 (0.201) 4.90 (0.193) 1.20 (0.047) max 0.65 (.0256) bsc 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) index mark 6.50 (0.256) 6.25 (0.246) seating plane 4.50 (0.177) 4.30 (0.169) pin 1 0.75 (0.030) 0.45 (0.018) 0o~ 8o 0.30 (0.012) 0.19 (0.007) dimensions in millimeters and (inches). controlling dimension: millimeters. jedec standard mo-153 ab-1. 215 8235b?avr?04/11 attiny20 25.3 15cc1 title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com r c cbc 15cc1, 15- ba ll (4 x 4 arr a y), 3 .0 x 3 .0 x 0.6 mm p a ck a ge, ba ll pitch 0.65 mm, ultr a thin, fine-pitch b a ll grid arr a y p a ck a ge (ufbga) 15cc1 07/06/10 a ? ? 0.60 a1 0.12 ? ? a2 0. 38 ref b 0.25 0. 3 0 0. 3 5 1 b 1 0.25 ? ? 2 d 2.90 3 .00 3 .10 d1 1.95 b s c e 2.90 3 .00 3 .10 e1 1.95 b s c e 0.65 b s c common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note top view 12 3 4 a b c d e d 15-? b d c b a pin#1 id 0.0 8 a1 a d1 e1 a2 a1 ball corner e 12 3 4 s ide view b 1 bottom view e note1: dimension ?b? is measured at the maximum ball dia. in a plane parallel to the seating plane. note2: dimen s ion ?b 1 ? i s the s older ab le su rf a ce defined b y the opening of the solder resist layer. 216 8235b?avr?04/11 attiny20 25.4 20m2 title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 20m2 zfc b 20m2, 20-pad, 3 x 3 x 0.85 mm body, lead pitch 0.45 mm, 1.55 x 1.55 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 15 14 1 3 12 11 1 2 3 4 5 16 17 1 8 19 20 10 9 8 7 6 d2 e2 e b k l pin #1 ch a mfer (c 0. 3 ) d e s ide view a1 y pin 1 id bottom view top view a1 a c c0.1 8 ( 8 x) 0. 3 ref (4x) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.75 0. 8 0 0. 8 5 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.152 d 2.90 3 .00 3 .10 d2 1.40 1.55 1.70 e 2.90 3 .00 3 .10 e2 1.40 1.55 1.70 e ? 0.45 ? l 0. 3 5 0.40 0.45 k 0.20 ? ? y 0.00 ? 0.0 8 217 8235b?avr?04/11 attiny20 26. errata the revision letters in this section refer to the revision of the corresponding attiny20 device. 26.1 rev. a ? lock bits re-programming ? miso output driver is not di sabled by slave select (ss ) signal 1. lock bits re-programming attempt to re-program lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of flash program memory to get erased. the lock bits will not get changed, as they should not. problem fix / workaround do not attempt to re-program lock bits to present, or lower protection level. 2. miso output driver is not disabled by slave select (ss ) signal when spi is configured as a slave and the miso pin is configured as an output the pin out- put driver is constantly enabled, even when the ss pin is high. if other slave devices are connected to the same miso line this behaviour may cause drive contention. problem fix / workaround monitor ss pin by software and use the ddrb2 bit of ddrb to control the miso pin driver. 218 8235b?avr?04/11 attiny20 27. datasheet revision history 27.1 rev. 8235b ? 04/11 1. removed preliminary status 2. updated: ? bit syntax throughout the datasheet, e.g. from cs02:0 to cs0[2:0] ? idle mode description on page 5 ? ?capacitive touch sensing? on page 6 (section updated and moved) ? ?disclaimer? on page 6 ? sentence on low impedance sources in ?analog input circuitry? on page 119 ? description on 16-bit registers on page 8 ? description on stack pointer on page 10 ? list of active modules in ?idle mode? on page 25 ? description on reset pulse width in ?watchdog reset? on page 32 ? program code on page 39 ? bit description in figure 11-3 on page 63 ? section ?compare output mode and waveform generation? on page 65 ? signal descriptions in figure 11-5 on page 66 , and figure 11-7 on page 68 ? equations on page 66 , page 67 , and page 69 ? terminology in sections describing extreme values on page 67 , and page 69 ? description on creating frequency waveforms on page 69 ? signal routing in figure 12-1 on page 78 ? top definition in table 12-1 on page 79 ? signal names in figure 12-3 on page 81 ? twshe bit description in ?twscra ? twi slave control register a? on page 146 ? spi slave assembly code example on page 132 ? table 20-1 on page 172 ? section ?speed? on page 174 ? characteristics in figure 21-3 on page 181 , and figure 21-8 on page 184 3. added: ? note on internal voltage reference in table 15-4 on page 124 ? pradc in table 21-2 on page 180 ? miso output driver errata for device rev. a in ?errata? on page 217 27.2 rev. 8235a ? 03/10 1. initial revision. i 8235b?avr?04/11 attiny20 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1 pin description ..................................................................................................2 2 overview ............ ................ ................ ............... .............. .............. ............ 4 3 general information ............ .............. ............... .............. .............. ............ 6 3.1 resources .........................................................................................................6 3.2 code examples .................................................................................................6 3.3 capacitive touch sensing .................................................................................6 3.4 data retention ...................................................................................................6 3.5 disclaimer ..........................................................................................................6 4cpu core ............... .............. .............. ............... .............. .............. ............ 7 4.1 architectural overview .......................................................................................7 4.2 alu ? arithmetic logic unit ...............................................................................8 4.3 status register ..................................................................................................8 4.4 general purpose register file ..........................................................................9 4.5 stack pointer ...................................................................................................10 4.6 instruction execution timing ...........................................................................10 4.7 reset and interrupt handling ...........................................................................11 4.8 register description ........................................................................................13 5 memories ............... .............. .............. ............... .............. .............. .......... 15 5.1 in-system re-programmable flash program memory ....................................15 5.2 data memory ...................................................................................................15 5.3 i/o memory ......................................................................................................17 6 clock system ........... ................ ................ ................. ................ ............. 18 6.1 clock subsystems ...........................................................................................18 6.2 clock sources .................................................................................................19 6.3 system clock prescaler ..................................................................................20 6.4 starting ............................................................................................................20 6.5 register description ........................................................................................22 7 power management and sleep mo des ............... .............. ............ ........ 25 7.1 sleep modes ....................................................................................................25 7.2 software bod disable .....................................................................................26 ii 8235b?avr?04/11 attiny20 7.3 power reduction register ...............................................................................27 7.4 minimizing power consumption ......................................................................27 7.5 register description ........................................................................................28 8 system control and reset ...... ................ ................. ................ ............. 30 8.1 resetting the avr ...........................................................................................30 8.2 reset sources .................................................................................................30 8.3 internal voltage reference ..............................................................................33 8.4 watchdog timer ..............................................................................................33 8.5 register description ........................................................................................35 9 interrupts ........ ................. ................ ................. .............. .............. .......... 38 9.1 interrupt vectors ..............................................................................................38 9.2 external interrupts ...........................................................................................39 9.3 register description ........................................................................................41 10 i/o ports ............... ................ .............. ............... .............. .............. .......... 44 10.1 overview ..........................................................................................................44 10.2 ports as general digital i/o .............................................................................45 10.3 alternate port functions ..................................................................................49 10.4 register description ........................................................................................58 11 8-bit timer/counter0 with pw m .............. ................. ................ ............. 60 11.1 features ..........................................................................................................60 11.2 overview ..........................................................................................................60 11.3 clock sources .................................................................................................61 11.4 counter unit ....................................................................................................61 11.5 output compare unit .......................................................................................62 11.6 compare match output unit ............................................................................64 11.7 modes of operation .........................................................................................65 11.8 timer/counter timing diagrams .....................................................................69 11.9 register description ........................................................................................71 12 16-bit timer/counter1 ......... .............. ............... .............. .............. .......... 78 12.1 features ..........................................................................................................78 12.2 overview ..........................................................................................................78 12.3 timer/counter clock sources .........................................................................80 12.4 counter unit ....................................................................................................80 12.5 input capture unit ...........................................................................................81 iii 8235b?avr?04/11 attiny20 12.6 output compare units .....................................................................................83 12.7 compare match output unit ............................................................................85 12.8 modes of operation .........................................................................................86 12.9 timer/counter timing diagrams .....................................................................93 12.10 accessing 16-bit registers ..............................................................................95 12.11 register description ........................................................................................99 13 timer/counter prescaler ....... ................ ................. ................ ............. 105 13.1 prescaler reset .............................................................................................105 13.2 external clock source ...................................................................................105 13.3 register description ......................................................................................107 14 analog comparator .......... .............. .............. .............. .............. ........... 108 14.1 analog comparator multiplexed input ...........................................................109 14.2 register description ......................................................................................109 15 analog to digital converter ............. ............... .............. .............. ........ 112 15.1 features ........................................................................................................112 15.2 overview ........................................................................................................112 15.3 operation .......................................................................................................113 15.4 starting a conversion ....................................................................................114 15.5 prescaling and conversion timing ................................................................115 15.6 changing channel or reference selection ...................................................118 15.7 adc noise canceler .....................................................................................119 15.8 analog input circuitry ....................................................................................119 15.9 noise canceling techniques .........................................................................120 15.10 adc accuracy definitions .............................................................................120 15.11 adc conversion result .................................................................................123 15.12 temperature measurement ...........................................................................123 15.13 register description ......................................................................................124 16 spi ? serial peripheral interface ......... .............. .............. ............ ........ 129 16.1 features ........................................................................................................129 16.2 overview ........................................................................................................129 16.3 ss pin functionality ......................................................................................133 16.4 data modes ...................................................................................................134 16.5 register description ......................................................................................135 17 twi ? two wire slave interface ............ ................. ................ ............. 138 iv 8235b?avr?04/11 attiny20 17.1 features ........................................................................................................138 17.2 overview ........................................................................................................138 17.3 general twi bus concepts ...........................................................................138 17.4 twi slave operation .....................................................................................144 17.5 register description ......................................................................................146 18 programming interface .......... ................ ................. ................ ............. 152 18.1 features ........................................................................................................152 18.2 overview ........................................................................................................152 18.3 physical layer of tiny programming interface ..............................................152 18.4 access layer of tiny programming interface ................................................156 18.5 instruction set ................................................................................................157 18.6 accessing the non-volatile memory controller .............................................160 18.7 control and status space register descriptions ..........................................160 19 memory programming ........ .............. ............... .............. .............. ........ 163 19.1 features ........................................................................................................163 19.2 overview ........................................................................................................163 19.3 non-volatile memories ..................................................................................164 19.4 accessing the nvm .......................................................................................167 19.5 self programming ..........................................................................................170 19.6 external programming ...................................................................................170 19.7 register description ......................................................................................170 20 electrical characteristics ... .............. ............... .............. .............. ........ 172 20.1 absolute maximum ratings* .........................................................................172 20.2 dc characteristics .........................................................................................172 20.3 speed ............................................................................................................174 20.4 clock characteristics .....................................................................................174 20.5 system and reset characteristics ................................................................175 20.6 analog comparator characteristics ...............................................................176 20.7 adc characteristics ......................................................................................177 20.8 serial programming characteristics ..............................................................177 21 typical characteristics ....... .............. ............... .............. .............. ........ 179 21.1 supply current of i/o modules ......................................................................179 21.2 current consumption in active mode ............................................................180 21.3 current consumption in idle mode ................................................................183 21.4 current consumption in power-down mode ..................................................185 v 8235b?avr?04/11 attiny20 21.5 current consumption in reset ......................................................................186 21.6 current consumption of peripheral units ......................................................187 21.7 pull-up resistors ...........................................................................................189 21.8 output driver strength ...................................................................................192 21.9 input thresholds and hysteresis ...................................................................198 21.10 bod, bandgap and reset .............................................................................201 21.11 analog comparator offset .............................................................................205 21.12 internal oscillator speed ...............................................................................205 22 register summary ............ .............. .............. .............. .............. ........... 208 23 instruction set summary ... .............. ............... .............. .............. ........ 210 24 ordering information .......... .............. ............... .............. .............. ........ 212 24.1 attiny20 ........................................................................................................212 25 packaging information .......... ................ ................. ................ ............. 213 25.1 14s1 ..............................................................................................................213 25.2 14x ................................................................................................................214 25.3 15cc1 ...........................................................................................................215 25.4 20m2 ..............................................................................................................216 26 errata ........... ................ ................ ................. ................ .............. ........... 217 26.1 rev. a ............................................................................................................217 27 datasheet revision history .. ................ ................. ................ ............. 218 27.1 rev. 8235b ? 04/11 .......................................................................................218 27.2 rev. 8235a ? 03/10 .......................................................................................218 table of contents.......... ................. ................ ................. ................ ........... i 8235b?avr?04/11 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81)(3) 3523-3551 fax: (+81)(3) 3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2011 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others ar e registered trademarks or trademarks of at mel corporation or its subsidiaries. o ther terms and product names may be trademarks of others. |
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